Method of transferring burst data in a microprocessor

Claim 1

A microprocessor system including a microprocessor and an external memory device, said microprocessor having an internal bus of width W bits coupled to an external bus accomodating transfer of a data line of length L bits, said data line including a plurality of data items, said microprocessor system being adapted to transfer said plurality of data items in a burst format from said external memory device via said external bus to said internal bus, said microprocessor system comprising: an address generator for generating a first address, A 0 , for accessing in said external memory device a first data item of said data line; an address sequence generator for generating a sequence of remaining addresses for accessing remaining ones of said data items of said data line, wherein said sequence of remaining addresses is generated according to A.sub.i =A.sub.0 ⊕(i*(W/8)), where A i represents one of said remaining addresses in said sequence and wherein i=1, 2, . . . ((L/W)-1) and L and W are integers; wherein said external memory device transfers to said microprocessor said first data item corresponding to said first address, A 0 , and wherein said external memory device transfers to said microprocessor in a burst format said remaining ones of said data items in an order corresponding to said sequence of remaining addresses.

Claim 7

A method for operating a microprocessor, said microprocessor having an internal bus of width W bits coupled to an external bus accomodating transfer of a data line of length L bits, said data line including a plurality of data items, said method including transferring said plurality of data items in burst format from said external bus to said internal bus, and comprising the steps of: issuing a first address, A O , by said microprocessor to access a first data item of said data line; generating a sequence of remaining addresses representing remaining ones of said data items of said data line other than said first data item, wherein said sequence of remaining addresses is generated according to A.sub.i =A.sub.O ⊕(i*(W/8)), where A i represents one of said remaining addresses in said sequence and wherein i=1,2, . . . ((L/W)-1) and L and W are integers; and receiving on said internal bus from said external bus said first data item and said remaining one of said data items.

Claim 8

A method for operating a microprocessor, said microprocessor having an internal bus of width W bits coupled to an external bus accomodating transfer of a data line of length L bits, said data line including a plurality of data items, said method including transferring said plurality of data items in burst format from said external bus to said internal bus, and comprising the steps of: issuing a first address, A O , by said microprocessor to access a first data item of said data line; generating a sequence of remaining addresses representing remaining ones of said data items of said data line other than said first data item, wherein said sequence of remaining addresses is generated according to A.sub.i =A.sub.O ⊕(i*(W/8)), where A i represents one of said remaining addresses in said sequence and wherein i=1,2, . . . ((L/W)-1) and L and W are integers; and receiving on said internal bus from said external bus said first data item and said remaining one of said data items.

Claim 12

A device for transferring L bits of data as a plurality of data items in burst format to a microprocessor having an internal data bus of width W bits via an external data bus in response to a first address signal, A O , wherein said first address signal corresponds to a first data item, the device comprising: circuitry for generating a sequence of remaining addresses representing remaining ones of said data items other than said first data item, wherein said sequence of remaining addresses is generated according to A i =A O ⊕(i* (W/8)), where A i represents one of said remaining addresses in said sequence and wherein i=1,2, . . . ((L/W)-1) and L and W are integers; and circuitry for receiving said first address signal and said remaining addresses and providing the first data item and said remaining ones of said data items to said external bus.

Claim 13

A device for transferring L bits of data as a plurality of data items in burst format to a microprocessor having an internal data bus of width W bits via an external data bus in response to a first address signal, A O , wherein said first address signal corresponds to a first data item, the device comprising: circuitry for generating a sequence of remaining addresses representing remaining ones of said data items other than said first data item, wherein said sequence of remaining addresses is generated according to A i =A O ⊕(i* (W/8)), where A i represents one of said remaining addresses in said sequence and wherein i=1,2, . . . ((L/W)-1) and L and W are integers; and circuitry for receiving said first address signal and said remaining addresses and providing the first data item and said remaining ones of said data items to said external bus.