Automatic bus setting, sensing and switching interface unit

Claim 2

An automatic bus setting, sensing and switching interface apparatus for configuring a first integrated circuit to interface with other integrated circuits via a selected one of a plurality of bus structures, the integrated circuit having a plurality of pins coupled to a bus, wherein there is no identity of a function and mode assigned for all the pins for any one of the bus structures relative to another bus structure, the apparatus comprising: a. a sensor for detecting a logic level of a single bus signal representative of the selected one of the bus structures to be used, the sensor coupled to the first integrated circuit; and b. a logic structure coupled to the sensor and to the first integrated circuit for automatically configuring the first integrated circuit to communicate with the other integrated circuits according to the selected one of the bus structures wherein at least one of the pins has a different function and mode for one selection of bus structure than for another selection of bus structure.

Claim 3

The apparatus as claimed in claim 1 wherein the plurality of bus structures is comprised of three bus structures, including an ISA bus structure, a PI bus structure and a Local bus structure.

Claim 4

The apparatus as claimed in claim 2 wherein the logic level for an ISA bus structure is a logical low voltage, the logic level for a PI bus structure is a logical high voltage and the logic level for a Local bus structure is a transition between a logical low voltage and a logical high voltage.

Claim 5

The apparatus as claimed in claim 3 wherein the logic structure for automatically configuring the first integrated circuit is comprised of an interface unit coupled to the first integrated circuit.

Claim 6

The apparatus as claimed in claim 4 wherein the interface unit for a local bus structure is configured for a 1X clock and a 16 bit data width.

Claim 7

An automatic bus setting, sensing and switching interface apparatus for configuring a first integrated circuit to interface with other integrated circuits via a selected one of a plurality of bus structures, the integrated circuit having a plurality of pins coupled to a bus, wherein there is no identity of a function and mode assigned for all the pins for any one of the bus structures relative to another bus structure, the apparatus comprising: a. a register for storing a code representative of parameters of the selected one of the bus structures to be used wherein the code is written into the register by a system BIOS, the register coupled to the first integrated circuit; and b. a logic structure coupled to the register and to the first integrated circuit for automatically configuring the first integrated circuit to communicate with the other integrated circuits according to the parameters of the selected one of the bus structures wherein at least one of the pins has a different function and mode for one selection of bus structure than for another selection of bus structure.

Claim 8

An automatic bus setting, sensing and switching interface apparatus for configuring a first integrated circuit to interface with other integrated circuits via a selected one of a plurality of bus structures, the integrated circuit having a plurality of pins coupled to a bus, wherein there is no identity of a function and mode assigned for all the pins for any one of the bus structures relative to another bus structure, the apparatus comprising: a. a register for storing a code representative of parameters of the selected one of the bus structures to be used wherein the code is written into the register by a system BIOS, the register coupled to the first integrated circuit; and b. a logic structure coupled to the register and to the first integrated circuit for automatically configuring the first integrated circuit to communicate with the other integrated circuits according to the parameters of the selected one of the bus structures wherein at least one of the pins has a different function and mode for one selection of bus structure than for another selection of bus structure.

Claim 9

The apparatus as claimed in claim 6 wherein the plurality of bus structures is comprised of three bus structures, including an ISA bus structure, a PI bus structure and a Local bus structure.

Claim 10

The apparatus as claimed in claim 7 wherein the logic structure for automatically configuring the first integrated circuit is comprised of an interface unit coupled to the first integrated circuit.

Claim 11

The apparatus as claimed in claim 8 wherein the interface unit for a local bus structure can be configured to either a 16 bit data width or a 32 bit data width as specified by the code.

Claim 12

The apparatus as claimed in claim 9 wherein the interface unit for a local bus structure can be configured to either a 1X clock or a 2X clock as specified by the code.

Claim 13

An automatic bus setting, sensing and switching interface apparatus for configuring a first integrated circuit to interface with other integrated circuits via a selected one of a plurality of bus structures, the integrated circuit having a plurality of pins coupled to a bus, wherein there is no identity of a function and mode assigned for all the pins for any one of the bus structures relative to another bus structure, the apparatus comprising: a. a sensor for detecting a logic level of a single bus signal representative of the selected one of the bus structures to be used, the sensor coupled to the first integrated circuit; b. a register for storing a code representative of parameters of the selected one of the bus structures to be used wherein the code is written into the register by a system BIOS, the register coupled to the first integrated circuit; and c. a logic structure coupled to the register and to the first integrated circuit for automatically configuring the first integrated circuit to communicate with the other integrated circuits according to the parameters of the selected one of the bus structures wherein at least one of the pins has a different function and mode for one selection of bus structure than for another selection of bus structure.

Claim 14

An automatic bus setting, sensing and switching interface apparatus for configuring a first integrated circuit to interface with other integrated circuits via a selected one of a plurality of bus structures, the integrated circuit having a plurality of pins coupled to a bus, wherein there is no identity of a function and mode assigned for all the pins for any one of the bus structures relative to another bus structure, the apparatus comprising: a. a sensor for detecting a logic level of a single bus signal representative of the selected one of the bus structures to be used, the sensor coupled to the first integrated circuit; b. a register for storing a code representative of parameters of the selected one of the bus structures to be used wherein the code is written into the register by a system BIOS, the register coupled to the first integrated circuit; and c. a logic structure coupled to the register and to the first integrated circuit for automatically configuring the first integrated circuit to communicate with the other integrated circuits according to the parameters of the selected one of the bus structures wherein at least one of the pins has a different function and mode for one selection of bus structure than for another selection of bus structure.

Claim 15

The apparatus as claimed in claim 11 wherein the plurality of bus structures is comprised of three bus structures, including an ISA bus structure, a PI bus structure and a Local bus structure.

Claim 16

The apparatus as claimed in claim 12 wherein the logic level for an ISA bus structure is a logical low voltage, the logic level for a PI bus structure is a logical high voltage and the logic level for a Local bus structure is a transition between a logical low voltage and a logical high voltage.

Claim 17

The apparatus as claimed in claim 13 wherein the logic structure is comprised of an interface unit coupled to the first integrated circuit.

Claim 18

The apparatus as claimed in claim 14 wherein the interface unit for a local bus structure can be configured to either a 16 bit data width or a 32 bit data width as specified by the code.

Claim 19

The apparatus as claimed in claim 15 wherein the interface unit for a local bus structure can be configured to either a 1X clock or a 2X clock as specified by the code.

Claim 20

An automatic bus setting, sensing and switching interface apparatus for configuring a first integrated circuit to interface with other integrated circuits via a selected one of a plurality of bus structures, the integrated circuit having a plurality of pins coupled to a bus, wherein there is no identity of a function and mode assigned for all the pins for any one of the bus structures relative to another bus structure, the apparatus comprising: a. means for detecting a logic level of a single bus signal representative of the selected one of the bus structures to be used, the means for detecting coupled to the first integrated circuit; and b. means for automatically configuring the first integrated circuit to communicate with the other integrated circuits according to the selected one of the bus structures wherein at least one of the pins has a different function and mode for one selection of bus structure than for another selection of bus structure.

Claim 21

An automatic bus setting, sensing and switching interface apparatus for configuring a first integrated circuit to interface with other integrated circuits via a selected one of a plurality of bus structures, the integrated circuit having a plurality of pins coupled to a bus, wherein there is no identity of a function and mode assigned for all the pins for any one of the bus structures relative to another bus structure, the apparatus comprising: a. means for detecting a logic level of a single bus signal representative of the selected one of the bus structures to be used, the means for detecting coupled to the first integrated circuit; and b. means for automatically configuring the first integrated circuit to communicate with the other integrated circuits according to the selected one of the bus structures wherein at least one of the pins has a different function and mode for one selection of bus structure than for another selection of bus structure.

Claim 22

The apparatus as claimed in claim 17 wherein the plurality of bus structures is comprised of three bus structures, including an ISA bus structure, a PI bus structure and a Local bus structure.

Claim 23

The apparatus as claimed in claim 18 wherein the logic level for an ISA bus structure is a logical low voltage, the logic level for a PI bus structure is a logical high voltage and the logic level for a Local bus structure is a transition between a logical low voltage and a logical high voltage.

Claim 24

The apparatus as claimed in claim 19 wherein the means for automatically configuring the first integrated circuit is comprised of an interface unit coupled to the first integrated circuit.

Claim 25

The apparatus as claimed in claim 20 wherein the interface unit for a local bus structure is configured for a 1X clock and a 16 bit data width.

Claim 26

An automatic bus setting, sensing and switching interface apparatus for configuring a first integrated circuit to interface with other integrated circuits via a selected one of a plurality of bus structures, the integrated circuit having a plurality of pins coupled to a bus, wherein there is no identity of a function and mode assigned for all the pins for any one of the bus structures relative to another bus structure, the apparatus comprising: a. means for storing a code representative of parameters of the selected one of the bus structures to be used wherein the code is written into the means for storing by the system BIOS, the means for storing coupled to the first integrated circuit; and b. means for automatically configuring the first integrated circuit to communicate with the other integrated circuits according to the selected one of the bus structures.

Claim 27

An automatic bus setting, sensing and switching interface apparatus for configuring a first integrated circuit to interface with other integrated circuits via a selected one of a plurality of bus structures, the integrated circuit having a plurality of pins coupled to a bus, wherein there is no identity of a function and mode assigned for all the pins for any one of the bus structures relative to another bus structure, the apparatus comprising: a. means for storing a code representative of parameters of the selected one of the bus structures to be used wherein the code is written into the means for storing by the system BIOS, the means for storing coupled to the first integrated circuit; and b. means for automatically configuring the first integrated circuit to communicate with the other integrated circuits according to the selected one of the bus structures.

Claim 28

The apparatus as claimed in claim 22 wherein the plurality of bus structures is comprised of three bus structures, including an ISA bus structure, a PI bus structure and a Local bus structure.

Claim 29

The apparatus as claimed in claim 23 wherein the means for automatically configuring the first integrated circuit is comprised of an interface unit coupled to the first integrated circuit.

Claim 30

The apparatus as claimed in claim 24 wherein the interface apparatus for a local bus structure can be configured to either a 16 bit data width or a 32 bit data width as specified by the code.

Claim 31

The apparatus as claimed in claim 25 wherein the interface apparatus for a Local bus structure can be configured to either a 1X clock or a 2X clock as specified by the code.

Claim 32

The apparatus as claimed in claim 26 wherein the means for storing is comprised of a first storage register and a second storage register.

Claim 33

The apparatus as claimed in claim 27 wherein the first storage register is disabled after the code has been stored in the second storage register.

Claim 34

An automatic bus setting, sensing and switching interface apparatus for configuring a first integrated circuit to interface with other integrated circuits via a selected one of a plurality of bus structures, the integrated circuit having a plurality of pins coupled to a bus, wherein there is no identity of a function and mode assigned for all the pins for any one of the bus structures relative to another bus structure, the apparatus comprising: a. means for detecting a logic level of a single bus signal representative of the selected one of the bus structures to be used, the means for detecting coupled to the first integrated circuit; b. means for storing a code representative of parameters of the selected one of the bus structures to be used wherein the code is written into the means for storing by the system BIOS, the means for storing coupled to the first integrated circuit; and c. means for automatically configuring the first integrated circuit to communicate with the other integrated circuits according to the selected one of the bus structures wherein at least one of the pins has a different function and mode for one selection of bus structure than for another selection of bus structure.

Claim 35

An automatic bus setting, sensing and switching interface apparatus for configuring a first integrated circuit to interface with other integrated circuits via a selected one of a plurality of bus structures, the integrated circuit having a plurality of pins coupled to a bus, wherein there is no identity of a function and mode assigned for all the pins for any one of the bus structures relative to another bus structure, the apparatus comprising: a. means for detecting a logic level of a single bus signal representative of the selected one of the bus structures to be used, the means for detecting coupled to the first integrated circuit; b. means for storing a code representative of parameters of the selected one of the bus structures to be used wherein the code is written into the means for storing by the system BIOS, the means for storing coupled to the first integrated circuit; and c. means for automatically configuring the first integrated circuit to communicate with the other integrated circuits according to the selected one of the bus structures wherein at least one of the pins has a different function and mode for one selection of bus structure than for another selection of bus structure.

Claim 36

The apparatus as claimed in claim 29 wherein the plurality of bus structures is comprised of three bus structures, including an ISA bus structure, a PI bus structure and a Local bus structure.

Claim 37

The apparatus as claimed in claim 30 wherein the logic level for an ISA bus structure is a logical low voltage, the logic level for a PI bus structure is a logical high voltage and the logic level for a Local bus structure is a transition between a logical low voltage and a logical high voltage.

Claim 38

The apparatus as claimed in claim 31 wherein the means for automatically configuring the first integrated circuit is comprised of an interface unit coupled to the first integrated circuit.

Claim 39

The apparatus as claimed in claim 32 wherein the interface apparatus for a local bus structure can be configured to either a 16 bit data width or a 32 bit data width as specified by the code.

Claim 40

The apparatus as claimed in claim 33 wherein the interface apparatus for a Local bus structure can be configured to either a 1X clock or a 2X clock as specified by the code.

Claim 41

The apparatus as claimed in claim 34 wherein the means for storing is comprised of a first storage register and a second storage register.

Claim 42

The apparatus as claimed in claim 35 wherein the first storage register is disabled after the code has been stored in the second storage register.

Claim 45

The method as claimed in claim 37 wherein the plurality of bus structures includes an ISA bus structure, a PI bus structure and a local bus structure.

Claim 46

The method as claimed in claim 38 wherein the logic level for an ISA bus structure is a logical low voltage, the logic level for a PI bus structure is a logical high voltage and the logic level for a Local bus structure is a transition between a logical low voltage and a logical high voltage.

Claim 47

The method as claimed in claim 39 wherein the interface unit for a local bus structure is configured for a 1X clock and a 16 bit data width.

Claim 50

The method as claimed in claim 41 wherein the plurality of bus structures includes an ISA bus structure, a PI bus structure and a Local bus structure.

Claim 51

The method as claimed in claim 42 wherein the parameters represented by the code are a clock speed and a data width.

Claim 52

The method as claimed in claim 43 wherein the clock speed for a local bus structure can be either 1X or 2X and the data width can be either 16 bit or 32 bit as specified by the code.

Claim 55

The method as claimed in claim 45 wherein the plurality of bus structures includes an ISA bus structure, a PI bus structure and a Local bus structure.

Claim 56

The method as claimed in claim 46 wherein the logic level for an ISA bus structure is a logical low voltage, the logic level for a PI bus structure is a logical high voltage and the logic level for a Local bus structure is a transition between a logical low voltage and a logical high voltage.

Claim 57

The method as claimed in claim 47 wherein the parameters represented by the code are a clock speed and a data width.

Claim 58

The method as claimed in claim 48 wherein the clock speed for a Local bus structure can be either 1X or 2X and the data width can be either 16 bit or 32 bit as specified by the code.

Claim 59

An automatic bus setting, sensing and switching interface apparatus for configuring a first integrated circuit to interface with other integrated circuits via a selected one of a plurality of bus structures, the first integrated circuit having a predetermined number of pins, the integrated circuit having plurality of pins coupled to a bus, wherein there is no identity of a function and mode assigned for all the pins for any one of the bus structures relative to another bus structure, the apparatus comprising: a. a first pin for receiving a single bus signal representative of the selected one of the bus structures to be used, the first pin coupled to the first integrated circuit; b. a detection signal logic structure for detecting a logic level of the bus signal received by the first pin, the detection signal logic structure coupled to the first pin; c. a first storage register for storing a code, the code representing parameters of the selected one of the bus structures to be used, the first storage register coupled to the first integrated circuit; d. a second storage register for storing the code from the first storage register, the second storage register coupled to the first storage register; and e. a configuration signal logic structure for storing the code from the first storage register into the second storage register and automatically configuring the interface apparatus and the pins of the first integrated circuit to interface via the selected one of the bus structures wherein the configuration signal logic structure is coupled to the integrated circuit wherein at least one of the pins has a different function and mode for one selection of bus structure than for another selection of bus structure.

Claim 60

An automatic bus setting, sensing and switching interface apparatus for configuring a first integrated circuit to interface with other integrated circuits via a selected one of a plurality of bus structures, the first integrated circuit having a predetermined number of pins, the integrated circuit having plurality of pins coupled to a bus, wherein there is no identity of a function and mode assigned for all the pins for any one of the bus structures relative to another bus structure, the apparatus comprising: a. a first pin for receiving a single bus signal representative of the selected one of the bus structures to be used, the first pin coupled to the first integrated circuit; b. a detection signal logic structure for detecting a logic level of the bus signal received by the first pin, the detection signal logic structure coupled to the first pin; c. a first storage register for storing a code, the code representing parameters of the selected one of the bus structures to be used, the first storage register coupled to the first integrated circuit; d. a second storage register for storing the code from the first storage register, the second storage register coupled to the first storage register; and e. a configuration signal logic structure for storing the code from the first storage register into the second storage register and automatically configuring the interface apparatus and the pins of the first integrated circuit to interface via the selected one of the bus structures wherein the configuration signal logic structure is coupled to the integrated circuit wherein at least one of the pins has a different function and mode for one selection of bus structure than for another selection of bus structure.

Claim 61

The apparatus as claimed in claim 50 wherein the plurality of data bus structures is comprised of three bus structures, including an ISA bus structure, a PI bus structure and a Local bus structure.

Claim 62

The apparatus as claimed in claim 51 wherein the logic level for an ISA bus structure is a logical low voltage, the logic level for a PI bus structure is a logical high voltage and the logic level for a Local bus structure is a transition between a logical low voltage and a logical high voltage.

Claim 63

The apparatus as claimed in claim 52 wherein the interface apparatus for a Local bus structure can be configured to either a 16 bit data width or a 32 bit data width as specified by the code.

Claim 64

The apparatus as claimed in claim 53 wherein the interface apparatus for a Local bus structure can be configured to either a 1X clock or a 2X clock as specified by the code.

Claim 65

The apparatus as claimed in claim 50 wherein the configuration signal logic structure also disables the first storage register after the code has been stored in the second storage register.

Claim 68

The method as claimed in claim 56 further comprising the step of disabling the first storage register after storing the code from the first storage register into the second storage register.

Claim 69

The method as claimed in claim 57 wherein the code represents the data width to be used if the interface is configured for a Local bus structure.

Claim 70

The method as claimed in claim 58 wherein the code further represents the clock speed to be used if the interface is configured for a Local bus structure.