US5280587A — Computer system in which a bus controller varies …

Claim 1

Independent Claim 275 words

A computer system comprising: a bus; a plurality of devices connected to the bus, each of the plurality of devices for receiving and transmitting data over the bus at one of a plurality of data transfer rates; and, a bus controller, connected to the bus, the bus controller including; a central processing unit, which generates addresses identifying one of the plurality of devices for a data transfer, address lines, connected to the central processing unit, which receives address bits generated by the central processing unit, a first data transfer rate being encoded on a first set of the address lines, a storage device for storing a first stored value which indicates a second data transfer rate, selection means, having a first input connected to the first set of the address lines, having a second input connected to the storage device and having an output, for selecting either the first stored value on the second input or the encoded first data rate on the first input to be connected to the output, and control signal generator means, having an input connected to the output of the selection means, for generating bus control signals which control data transfer over the bus, the control signals controlling data transfer rate over the bus; wherein when the selection means selects the first input, the control signal generator means generates the bus control signals such that data is transferred over the bus at the first data transfer rate and when the selection means selects the second input, the control signal generator means generates the bus control signals such that data is transferred over the bus at the second data transfer rate.

Claim 2

Dependent Claim 275 words

A computer system comprising: a bus; a plurality of devices connected to the bus, each of the plurality of devices for receiving and transmitting data over the bus at one of a plurality of data transfer rates; and, a bus controller, connected to the bus, the bus controller including; a central processing unit, which generates addresses identifying one of the plurality of devices for a data transfer, address lines, connected to the central processing unit, which receives address bits generated by the central processing unit, a first data transfer rate being encoded on a first set of the address lines, a storage device for storing a first stored value which indicates a second data transfer rate, selection means, having a first input connected to the first set of the address lines, having a second input connected to the storage device and having an output, for selecting either the first stored value on the second input or the encoded first data rate on the first input to be connected to the output, and control signal generator means, having an input connected to the output of the selection means, for generating bus control signals which control data transfer over the bus, the control signals controlling data transfer rate over the bus; wherein when the selection means selects the first input, the control signal generator means generates the bus control signals such that data is transferred over the bus at the first data transfer rate and when the selection means selects the second input, the control signal generator means generates the bus control signals such that data is transferred over the bus at the second data transfer rate.

Claim 3

Dependent Claim 38 words

A computer system as in claim 1 wherein the bus controller additionally comprises: arbiter means, connected to the selection means, for directing the selection means as to which of the first input and the second output to select.

Claim 4

Dependent Claim 50 words

A computer system as in claim 1 wherein the storage device is additionally for storing a second stored value which indicates a second data transfer rate and the multiplexor means is also for selecting the second stored value to be coupled to the input of the control signal generator means.

Claim 5

Dependent Claim 54 words

A computer as in claim 1 wherein the computer system generates a clock signal used in data transfers over the bus and the control signal generator means generates the bus control signals such that the first data transfer rate varies from the second data transfer rate in number of clock cycles per datum transfer.

Claim 6

Dependent Claim 175 words

In a computer system which includes a bus and a plurality of devices coupled to the bus, a method comprising the steps of: (a) when performing a data transfer over the bus, controlled by a bus controller, to or from a first device, performing the following substeps: (a.1) generating addresses by a CPU within the bus controller, and (a.2) generating, by the bus controller, control signals which control the data transfer, a data transfer rate of the data transfer being based on a subset of address bits within an address used to address the first device, the first subset of address bits being reserved to indicate data transfer rate; and, (b) when performing a first DMA data transfer in a first DMA channel, performing the following substeps: (b.1) generating addresses for the first DMA data transfer, and (b.2) generating, by the bus controller, first control signals for the first DMA data transfer, a first data transfer rate for the first DMA data transfer being based on a first stored value stored in a storage device.

Claim 7

Dependent Claim 175 words

In a computer system which includes a bus and a plurality of devices coupled to the bus, a method comprising the steps of: (a) when performing a data transfer over the bus, controlled by a bus controller, to or from a first device, performing the following substeps: (a.1) generating addresses by a CPU within the bus controller, and (a.2) generating, by the bus controller, control signals which control the data transfer, a data transfer rate of the data transfer being based on a subset of address bits within an address used to address the first device, the first subset of address bits being reserved to indicate data transfer rate; and, (b) when performing a first DMA data transfer in a first DMA channel, performing the following substeps: (b.1) generating addresses for the first DMA data transfer, and (b.2) generating, by the bus controller, first control signals for the first DMA data transfer, a first data transfer rate for the first DMA data transfer being based on a first stored value stored in a storage device.

Claim 8

Dependent Claim 76 words

A method as in claim 5 additionally comprising the step of: (c) when performing a second DMA data transfer in a second DMA channel, performing the following substeps: (c.1) generating addresses for the second DMA data transfer; and, (c.2) generating, by the bus controller, second control signals for the second DMA data transfer, a second DMA data transfer rate for the second DMA data transfer being based on a second stored value in the storage device.

Claim 9

Dependent Claim 55 words

A method as in claim 6 wherein the computer system generates a clock signal used in data transfers over the bus and the data transfer rate in substep (a.2), the first data transfer rate in substep (b.2) and the second data transfer rate in substep (c.2), vary in number of clock cycles per datum transfer.

Claim 10

Dependent Claim 184 words

In a computer system which includes a bus, a bus controller and a plurality of devices coupled to the bus, a method comprising the steps of: (a) selecting, by the computer system, an address space for each device, including the substeps of: (a.1) assigning a block of address space for each device, and (a.2) dividing each block of address space into a plurality of sub-blocks, so that for an address formed of a plurality of address bits, a first subset of the plurality of address bits is used to identify a data transfer rate, and a third set of bits is used to designate a memory location within the peripheral device; and, (b) when performing a data transfers to and from a particular device from the plurality of devices, generating, by the bus controller, control signals for data transfers to and from the particular device, wherein the bus controller selects a data transfer rate, controlled by the control signals, for the data transfers based on a value of the second subset of the plurality of address bits for addresses used for the data transfers.

Claim 11

Dependent Claim 184 words

In a computer system which includes a bus, a bus controller and a plurality of devices coupled to the bus, a method comprising the steps of: (a) selecting, by the computer system, an address space for each device, including the substeps of: (a.1) assigning a block of address space for each device, and (a.2) dividing each block of address space into a plurality of sub-blocks, so that for an address formed of a plurality of address bits, a first subset of the plurality of address bits is used to identify a data transfer rate, and a third set of bits is used to designate a memory location within the peripheral device; and, (b) when performing a data transfers to and from a particular device from the plurality of devices, generating, by the bus controller, control signals for data transfers to and from the particular device, wherein the bus controller selects a data transfer rate, controlled by the control signals, for the data transfers based on a value of the second subset of the plurality of address bits for addresses used for the data transfers.

Claim 12

Dependent Claim 45 words

A method as in claim 8 wherein in step (b) the computer system generates a clock signal used in data transfers over the bus and data transfer rates for data transfer over the bus differ based on a number of clock cycles per datum transfer.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	1997-01-17	1997-07-19	1998-01-18	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	2001-01-17	2001-07-19	2002-01-18	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	2005-01-17	2005-07-19	2006-01-18	$7700.00	Window Closed / Lapsed

Computer system in which a bus controller varies data transfer rate over a bus based on a value of a subset of address bits and on a stored value

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