Interleaved and sequential counter

Claim 2

A counter system for producing an output count, the system comprising: a first counter; a second counter coupled to at least a first output from said first counter, said second counter producing said output count; and a selection signal, input to said second counter, for selecting between an interleaved count format and a sequential count format for said output count.

Claim 3

The counter system of claim 1 wherein said second counter further comprises a latch.

Claim 4

The counter system of claim 1 wherein said first counter further comprises at least a first input line for defining a count length.

Claim 5

The counter system of claim 1 wherein said first counter further comprises a reset line for resetting said first counter.

Claim 6

The counter system of claim 1 wherein said first and said second counters are three bit binary counters.

Claim 7

The counter system of claim 1 wherein said first counter produces a three bit binary count and wherein said second counter is coupled to the two least significant bits of said three bit binary count.

Claim 10

The method of claim 7 further comprising the steps of: inputting, into said first counter, a burst count length; repeating said steps of generating said first output count and said second output count until said burst length is reached.

Claim 11

A burst length counter system for producing a series of n-bit address signals, said system having an n-bit starting address input, the system comprising: a first binary counter having a resettable count length, said first binary counter counting every cycle of an input clock signal and producing an output count; a second binary counter having inputs coupled to the least significant bits of said output count from said first binary counter and further receiving at least the three least significant bits of said starting address, said second binary counter producing at least a three bit portion of an output address; selection means, coupled to said second binary counter, for selecting between an interleaved output count format and a sequential output count format for said counter system; latching means for receiving the most significant bits of said starting address; and combination means for combining said three bit portion of said output address with said most significant bits of said starting address to produce an n-bit output address; wherein said second binary counter produces an output count based upon the output count format selected by said selection means.

Claim 12

A burst length counter system for producing a series of n-bit address signals, said system having an n-bit starting address input, the system comprising: a first binary counter having a resettable count length, said first binary counter counting every cycle of an input clock signal and producing an output count; a second binary counter having inputs coupled to the least significant bits of said output count from said first binary counter and further receiving at least the three least significant bits of said starting address, said second binary counter producing at least a three bit portion of an output address; selection means, coupled to said second binary counter, for selecting between an interleaved output count format and a sequential output count format for said counter system; latching means for receiving the most significant bits of said starting address; and combination means for combining said three bit portion of said output address with said most significant bits of said starting address to produce an n-bit output address; wherein said second binary counter produces an output count based upon the output count format selected by said selection means.

Claim 13

The counter system of claim 9 wherein said resettable count length is equal to 8.