US4536760A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Signal-envelope display system for a digital oscilloscope
Assignee: Micron Technology Inc
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Filing: 1982-10-15
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Granted: 1985-08-20
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Expires: 2002-10-15
Abstract
Abstract A signal-envelope display system for a digital oscilloscope includes a memory for storing minimum and maximum signal values in adjacent storage locations, an address counter for sequentially addressing the memory, and a control circuit for selectively inverting the least significant bit of the address count signal. The values retrieved from the memory are converted to analog values and a low-pass filter connects the analog values to provide a signal envelope display.
Inventors
- 👤 Luis J. Navarro
- 👤 Joseph R. Peter
- 👤 Bruce W. Blair
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 09:56
CPC Classifications
G; G01; G01R; G01R13/00; G01R13/20; G01R13/22
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
138 words
A display system for a digital oscilloscope in which for each spaced interval along a signal waveform a maximum and a minimum amplitude value are obtained to provide a sequence of max-min value pairs, comprising: memory means for storing ordered pairs of said maximum and minimum amplitude values such that said max-min pairs are stored in adjacent addressable storage locations; address counter means for providing a binary address count signal consisting of binary bits to address said memory means sequentially to retrieve said maximum and minimum values; control circuit means for selectively inverting the least significant bit of the address count signal thereby transposing the order of maximum and minimum values in each max-min value pair being retrieved from said memory means; means responsive to the retrieved sequence of max-min value pairs for generating a display signal therefrom.
Claim 2
Dependent Claim
138 words
A display system for a digital oscilloscope in which for each spaced interval along a signal waveform a maximum and a minimum amplitude value are obtained to provide a sequence of max-min value pairs, comprising: memory means for storing ordered pairs of said maximum and minimum amplitude values such that said max-min pairs are stored in adjacent addressable storage locations; address counter means for providing a binary address count signal consisting of binary bits to address said memory means sequentially to retrieve said maximum and minimum values; control circuit means for selectively inverting the least significant bit of the address count signal thereby transposing the order of maximum and minimum values in each max-min value pair being retrieved from said memory means; means responsive to the retrieved sequence of max-min value pairs for generating a display signal therefrom.
Claim 3
Dependent Claim
129 words
A display system in accordance with claim 1, wherein said control circuit means comprises in combination a NOR gate, an AND gate, and an OR gate, each gate having a first and second input and an output; wherein the outputs of said NOR gate and said AND gate are connected respectively to the first and second inputs of said OR gate, and the output of said OR gate is connected to a least significant bit address terminal of said memory means; and further wherein the first inputs of said NOR gate and said AND gate are connected together to the least significant bit output of said address counter means, and the second inputs of said NOR gate and said AND gate are connected together to a control signal input.
Claim 4
Dependent Claim
106 words
A display system in accordance with claim 1, wherein said control circuit means comprises a multiplexer having a first input connected to the least significant bit output of said address counter means, and a second input connected to a output of an inverter whose input is also connected to the least significant bit output of said address counter means, wherein the output of said multiplexer is connected to the least significant bit address terminal of said memory means, and further wherein a control signal generated in response to a predetermined count from said address counter means is applied to said multiplexer to control input selection thereof.
Claim 5
Dependent Claim
53 words
A display system in accordance with claim 1, wherein said means for generating a display signal comprises a digital-to-analog converter for converting said retrieved sequence of max-min value pairs to analog values, and a low-pass filter connected to an output of said digital-to-analog converter for generating a signal which connects said analog values.
Claim 6
Dependent Claim
39 words
A display system in accordance with claim 2, wherein said control signal input connected to said second inputs of said NOR gate and said AND gate is generated in response to a predetermined count from said address counter means.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1988-08-19 | 1989-02-18 | 1989-08-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1992-08-19 | 1993-02-18 | 1993-08-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1996-08-19 | 1997-02-18 | 1997-08-20 | $7700.00 | Window Closed / Lapsed |