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US5593926A Expired / Lapsed US ⏱️ 0.0 years remaining

Method of manufacturing semiconductor device

Assignee: Sumitomo Electric Industries Ltd
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Filing: 1994-10-07
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Granted: 1997-01-14
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Expires: 2014-10-07
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Abstract

Abstract A method of manufacturing a semiconductor device having a package including a base, and a chip mounted on the base, wherein the chip has a surface on which an element is formed, the method comprising the steps of (a) fixing the chip having a protective coat formed on the surface to the base; and (b) removing the protective coat from the chip without touching the chip.

Inventors

  • 👤 Mitsuaki Fujihira

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-03 08:57
CPC Classifications
H; H10; H10P; H10P72/00; H10P72/04; H10P72/0402; H10P72/0404; H10P72/0441; H10P72/0444; H10W; H10W72/00; H10W72/071; H10W72/0711; H10W70/00; H10W70/60; H10W70/67; H10W70/68; H10W70/682; H10W72/01; H10W72/013; H10W72/01331; H10W72/0198; H10W72/073; H10W72/07302; H10W72/07304; H10W72/07331; H10W72/07337; H10W72/07338; H10W72/075; H10W72/30; H10W72/351; H10W72/352; H10W72/353; H10W72/354; H10W72/50; H10W72/551; H10W72/552; H10W72/5522; H10W72/5524; H10W72/851; H10W72/874; H10W72/884; H10W90/00; H10W90/701; H10W90/731; H10W90/734; H10W90/751; H10W90/753; H10W90/754; Y; Y10; Y10S; Y10S148/00; Y10S148/028

Claims Analysis

Total Claims: 10
Claim 1
Independent Claim 202 words
A method for manufacturing a semiconductor device, comprising the steps of: (a) forming first, second, and third wiring layers on a surface of a wafer, wherein said third wiring layer is arranged between said first and said second wiring layers; (b) coating surfaces of said first, second, and third wiring layers and a remaining exposed surface of said wafer with a resist; (c) partially removing said resist to expose a part of the surfaces of said first and second wiring layers; (d) coating said exposed surfaces of said first and second wiring layers, and a surface of said resist, with a fourth wiring layer to connect said first wiring layer to said second wiring layer via said fourth wiring layer; (e) removing said resist arranged between said fourth wiring layer and said third wiring layer to form an air gap between said third and fourth wiring layers, thereby forming an air bridge structure; (f) forming a chip from said wafer having said air bridge structure, said chip being covered with a protective coat; (g) die bonding said chip having said protective coat to a package; and (h) removing said protective coat from said chip while keeping said chip fixed on said package.
Claim 2
Independent Claim 202 words
A method for manufacturing a semiconductor device, comprising the steps of: (a) forming first, second, and third wiring layers on a surface of a wafer, wherein said third wiring layer is arranged between said first and said second wiring layers; (b) coating surfaces of said first, second, and third wiring layers and a remaining exposed surface of said wafer with a resist; (c) partially removing said resist to expose a part of the surfaces of said first and second wiring layers; (d) coating said exposed surfaces of said first and second wiring layers, and a surface of said resist, with a fourth wiring layer to connect said first wiring layer to said second wiring layer via said fourth wiring layer; (e) removing said resist arranged between said fourth wiring layer and said third wiring layer to form an air gap between said third and fourth wiring layers, thereby forming an air bridge structure; (f) forming a chip from said wafer having said air bridge structure, said chip being covered with a protective coat; (g) die bonding said chip having said protective coat to a package; and (h) removing said protective coat from said chip while keeping said chip fixed on said package.
Claim 3
Dependent Claim 57 words
A method according to claim 1, wherein said step (f) comprises the steps of: adhering said wafer on an adhesive tape; coating a surface of said wafer with said protective coat; dicing said wafer to form said chip, while keeping said protective coat thereon; and detaching said chip, coated with said protective coat, from said adhesive tape.
Claim 4
Dependent Claim 28 words
A method according to claim 1, wherein step (h) is performed by soaking said package in a solvent together with said chip, said solvent dissolving said protective coat.
Claim 5
Dependent Claim 28 words
A method according to claim 1, further comprising the step of drying said chip and said package by heating said base at a pressure lower than atmospheric pressure.
Claim 6
Independent Claim 215 words
A method of manufacturing a semiconductor device, comprising the steps of: (a) forming first, second, and third wiring layers on a surface of a wafer, wherein said third wiring layer is arranged between said first and said second wiring layers; (b) coating surfaces of said first, second, and third wiring layers and a remaining exposed surface of said wafer with a resist; (c) partially removing said resist to expose a part of the surfaces of said first and second wiring layers; (d) coating said exposed surfaces of said first and second wiring layers, and a surface of said resist with a fourth wiring layer to connect said first wiring layer to said second wiring layer via said fourth wiring layer; (e) removing said resist arranged between said fourth wiring layer and said third wiring layer to form an air gap between said third and fourth wiring layers, thereby forming an air bridge structure on said wafer; (f) forming a chip from said wafer having said air bridge structure, said chip being covered with a protective coat; (g) fixing said chip, having a surface coated with said protective coat, to a base; (h) removing said protective coat from said chip while keeping said chip fixed on said base; and (i) fixing said base to a package.
Claim 7
Independent Claim 215 words
A method of manufacturing a semiconductor device, comprising the steps of: (a) forming first, second, and third wiring layers on a surface of a wafer, wherein said third wiring layer is arranged between said first and said second wiring layers; (b) coating surfaces of said first, second, and third wiring layers and a remaining exposed surface of said wafer with a resist; (c) partially removing said resist to expose a part of the surfaces of said first and second wiring layers; (d) coating said exposed surfaces of said first and second wiring layers, and a surface of said resist with a fourth wiring layer to connect said first wiring layer to said second wiring layer via said fourth wiring layer; (e) removing said resist arranged between said fourth wiring layer and said third wiring layer to form an air gap between said third and fourth wiring layers, thereby forming an air bridge structure on said wafer; (f) forming a chip from said wafer having said air bridge structure, said chip being covered with a protective coat; (g) fixing said chip, having a surface coated with said protective coat, to a base; (h) removing said protective coat from said chip while keeping said chip fixed on said base; and (i) fixing said base to a package.
Claim 8
Dependent Claim 57 words
A method according to claim 5, wherein said step (f) comprises the steps of: adhering said wafer on an adhesive tape; coating a surface of said wafer with said protective coat; dicing said wafer to form said chip, while keeping said protective coat thereon; and detaching said chip, coated with said protective coat, from said adhesive tape.
Claim 9
Dependent Claim 28 words
A method according to claim 5, wherein step (h) is performed by soaking said base in a solvent together with said chip, said solvent dissolving said protective coat.
Claim 10
Dependent Claim 28 words
A method according to claim 5, further comprising the step of drying said chip and said base by heating said base at a pressure lower than atmospheric pressure.

References Cited (Backward Citations)

US3978578A Cited
US4263087A Cited
US4883773A Cited
US4833102A Cited
US4904610A Cited
US5100809A Cited
US5208178A Cited
US5358590A Cited
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USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 2000-01-14 2000-07-15 2001-01-14 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2004-01-14 2004-07-15 2005-01-14 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2008-01-14 2008-07-15 2009-01-14 $7700.00 Window Closed / Lapsed

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