Wafer level process for fabricating passivated semiconductor devices

Claim 2

A process for fabricating a plurality of semiconductor devices, said process comprising the steps of: mounting a semiconductor wafer on a substrate by an intervening layer of adhesive; cutting a multiplicity of grooves in the mounted wafer to form a plurality of chips, said grooves extending entirely through the wafer and partly through said layer of adhesive without extending into said substrate; putting a resinous bonding and passivating substance into said grooves, said substance at least partially filling portions of said grooves in both the adhesive layer and the wafer, to passivate, bond to, and interconnect the chips; and curing said substance.

Claim 3

A process as set forth in claim 1 further comprising the steps of: separating the substrate from the chips and said substance which bonds to the chips after the mounting, cutting, putting and curing steps whereby said chips and bonding substance form a discrete unit separate from said substrate; and after the separating step, applying heated solder to said plurality of chips and bonding substance while in said discrete unit at a temperature such that said bonding substance withstands the heat of said solder without losing its bond to the chips.

Claim 4

A process as set forth in claim 1 wherein the intervening layers of adhesive comprises wax.

Claim 5

A process as set forth in claim 1 wherein the cutting step comprises the step of cutting said grooves with a blade, and wherein said grooves are beveled such that sidewalls of the chips slope outwardly from a top, exposed surface of the chips.

Claim 6

A process as set forth in claim 1 wherein the cutting step comprises the step of chemically etching beveled grooves in said wafer.

Claim 7

A process as set forth in claim 1 wherein said substance which fills the spaces between the chips comprises a silicone resin which passivates the edges of said chips.

Claim 8

A process as set forth in claim 6 wherein said silicone resin is cured into a flexible state.

Claim 9

A process as set forth in claim 6 wherein said silicone resin is cured in a humid environment.

Claim 10

A process as set forth in claim 8 wherein said resin is cured in an environment having 20-50% relative humidity.

Claim 11

A process as set forth in claim 2 wherein said bonding substance comprises a silicone resin formulated to withstand heating to at least 350° C. without losing its bond to the chips.

Claim 12

A process as set forth in claim 10 wherein said silicone resin comprises iron oxide and acetoxysilane.

Claim 13

A process as set forth in claim 1 further comprising the step of electrode plating opposite faces of said wafer before the step of mounting said wafer onto said substrate, and wherein the cutting step includes the step of cutting the electrode plating into electrode portions which cover opposite faces of the chips.

Claim 14

A process as set forth in claim 12 wherein the step of putting said resinous substance into said grooves also includes the step of covering at least part of the exposed electrode portions on said chips with said substance.

Claim 15

A process as set forth in claim 13 wherein said substance is applied to the exposed electrode portions and put into the grooves by using a squeegee to draw the substance across the cut semiconductor wafer.

Claim 16

A process as set forth in claim 14 wherein the bonding substance comprises a silicone resin.

Claim 17

A process as set forth in claim 15 further comprising the step of removing the cured silicone resin from said electrode portions by a mechanical buffing operation.

Claim 18

A process as set forth in claim 16 wherein the removal step comprises the step of rubbing said cured silicone resin off said electrode portions using a rubber eraser.

Claim 19

A process as set forth in claim 1 further comprising the step of forming said wafer from silicon.

Claim 20

A process as set forth in claim 3 further comprising the steps of separating the substrate from the chips and said substance which bonds to the chips by melting away said wax using heat, and then chemically dissolving any wax remaining after the melting step.

Claim 21

A process as set forth in claim 19 wherein trichloroethylene is used to chemically dissolve said remaining wax.

Claim 22

A process as set forth in claim 1 further comprising the step of applying electrodes to the opposite faces of said wafer before the step of mounting said wafer on said substrate.

Claim 23

A process as set forth in claim 2 wherein said solder is applied by dipping said discrete unit of chips and bonding substance into a solder bath.

Claim 24

A process as set forth in claim 22 wherein said bonding substance comprises a silicone resin.

Claim 25

A process as set forth in claim 23 wherein said silicone resin is a type which can withstand heating to at least 350° C. by said solder bath without losing its adhesion to the chips.

Claim 26

A process as set forth in claim 2 further comprising the step of separating said chips from each other after the solder is applied while retaining a layer of the bonding substance on the edges of the chips.

Claim 27

A process as set forth in claim 25 wherein said bonding substance comprises a silicone resin.

Claim 28

A process as set forth in claim 2 further comprising the subsequent steps of placing said discrete unit with solder onto an adhesive surface and separating the chips from each other while retaining a layer of the bonding substance on the edges of the chips.

Claim 29

A process as set forth in claim 27 wherein the step of separating the chips from each other comprises the step of mechanically cutting through said bonding substance between the chips.

Claim 30

A process as set forth in claim 27 wherein the step of separating said chips from each other comprises the step of cutting the bonding substance between the chips with a laser beam.

Claim 31

A process as set forth in claim 1 further comprising the step of diffusing impurities into said wafer to form a p-n layer.

Claim 32

A process as set forth in claim 1 further comprising the step of etching the edges of the chips with an acid before the step of putting the resinous substance into the grooves between the chips and in the adhesive layer.

Claim 33

A process as set forth in claim 31 wherein said acid is a hydrofluoric-nitric-phosphoric acid mixture.

Claim 34

A process as set forth in claim 31 wherein the intervening adhesive layer comprises wax, and said wax is a type which is resistant to the acid used in the etching step and does not attack said substance which bonds to the chips.

Claim 35

A process as set forth in claim 33 wherein said substance which bonds to the chips is a silicone resin and said wax is a type which dissolves in trichlorethylene.

Claim 36

A process as set forth in claim 33 further comprising the step of separating the substrate from the chips and said substance which bonds to the chips by chemically dissolving said layer of wax.

Claim 37

A process as set forth in claim 35 wherein said layer of wax is chemically dissolved using trichlorethylene.

Claim 38

A process for fabricating a multiplicity of semiconductor devices, said process comprising the steps of: applying electrodes to both faces of a semiconductor wafer; mounting said semiconductor wafer on a substrate by means of an intervening layer of adhesive which bonds to the substrate and to the wafer; dividing the wafer while mounted into a multiplicity of chips by forming grooves which extend through the wafer and partly through said layer of adhesive without extending into said substrate; putting a resin into said grooves which passivates sidewalls of the chips, bonds to the sidewalls of said chips and interconnects said chips; curing said resin; separating said cured resin and chips from said substrate, whereby said chips and cured resin form a discrete unit separate from said substrate; after the separating step, applying heated, melted solder to said chips and bonding substance while in said discrete unit at such a temperature that said cured resin withstands the heat of said solder; and after the solder is applied, dividing said discrete unit with applied solder into cells, each cell including one of said chips and applied portion of the solder.

Claim 39

A process for fabricating a multiplicity of semiconductor devices, said process comprising the steps of: applying electrodes to both faces of a semiconductor wafer; mounting said semiconductor wafer on a substrate by means of an intervening layer of adhesive which bonds to the substrate and to the wafer; dividing the wafer while mounted into a multiplicity of chips by forming grooves which extend through the wafer and partly through said layer of adhesive without extending into said substrate; putting a resin into said grooves which passivates sidewalls of the chips, bonds to the sidewalls of said chips and interconnects said chips; curing said resin; separating said cured resin and chips from said substrate, whereby said chips and cured resin form a discrete unit separate from said substrate; after the separating step, applying heated, melted solder to said chips and bonding substance while in said discrete unit at such a temperature that said cured resin withstands the heat of said solder; and after the solder is applied, dividing said discrete unit with applied solder into cells, each cell including one of said chips and applied portion of the solder.

Claim 40

A process as set forth in claim 37 wherein said adhesive comprises wax and the separating step comprises the step of chemically dissolving the wax.

Claim 41

A process as set forth in claim 37 wherein the step of dividing said discrete unit into cells comprises the step of separating the chips from each other while retaining a layer of said cured resin around the edges of said chips to passivate the edges of said chips.

Claim 42

A process as set forth in claim 37 wherein the solder is applied by dipping said discrete unit in a solder bath.

Claim 43

A process as set forth in claim 37 comprising the further step of: etching said grooves to smooth them prior to said putting step.

Claim 44

A process as set forth in claim 37 wherein said resin is a silicone resin.

Claim 45

A process as set forth in claim 37 wherein the wafer is divided by a bevel cut whereby the sidewalls of the chips slope outwardly from exposed top surfaces of the chips.