Clock speed limiter for an integrated circuit

Claim 1

An apparatus for disabling the operation of an integrated circuit operating under control of an input clock signal, said apparatus comprising: a timing reference generator generating a timing reference having a frequency that is substantially constant with temperature, wherein the timing reference generator generates the timing reference using a bandgap voltage reference and a constant current reference; and a comparison circuit coupled to receive the timing reference and the input clock signal comparing a predetermined frequency to the input clock signal during a predetermined logic state of the timing reference and providing a disable signal for disabling the integrated circuit when the frequency of the input clock signal exceeds the predetermined frequency.

Claim 2

An apparatus for disabling the operation of an integrated circuit operating under control of an input clock signal, said apparatus comprising: a timing reference generator generating a timing reference having a frequency that is substantially constant with temperature, wherein the timing reference generator generates the timing reference using a bandgap voltage reference and a constant current reference; and a comparison circuit coupled to receive the timing reference and the input clock signal comparing a predetermined frequency to the input clock signal during a predetermined logic state of the timing reference and providing a disable signal for disabling the integrated circuit when the frequency of the input clock signal exceeds the predetermined frequency.

Claim 4

An apparatus for disabling the operation of an integrated circuit operating under control of an input clock signal, said apparatus comprising: a timing reference generator generating a timing reference having a frequency that is substantially constant with temperature, wherein the timing reference generator comprises a capacitor; a constant current source coupled to charge the capacitor, such that the capacitor generates a first potential; a trip point reference generating a second potential; a comparator coupled to compare the first potential and the second potential to produce an output, wherein the output is in a first state while the second potential exceeds the first potential and flips to a second state when the first potential exceeds the second potential; a discharge mechanism coupled to the capacitor and responsive to the output of the comparator to discharge the capacitor when the output is in the second state, such that the output flips back to the first state; and a comparison circuit coupled to receive the timing reference and the input clock signal comparing a predetermined frequency to the input clock signal during a predetermined logic state of the timing reference and providing a disable signal for disabling the integrated circuit when the frequency of the input clock signal exceeds the predetermined frequency, wherein the charging and discharging occur repeatedly to generate a stable frequency at the output of the comparison circuit, upon which the timing reference is based.

Claim 5

An apparatus for disabling the operation of an integrated circuit operating under control of an input clock signal, said apparatus comprising: a timing reference generator generating a timing reference having a frequency that is substantially constant with temperature, wherein the timing reference generator comprises a capacitor; a constant current source coupled to charge the capacitor, such that the capacitor generates a first potential; a trip point reference generating a second potential; a comparator coupled to compare the first potential and the second potential to produce an output, wherein the output is in a first state while the second potential exceeds the first potential and flips to a second state when the first potential exceeds the second potential; a discharge mechanism coupled to the capacitor and responsive to the output of the comparator to discharge the capacitor when the output is in the second state, such that the output flips back to the first state; and a comparison circuit coupled to receive the timing reference and the input clock signal comparing a predetermined frequency to the input clock signal during a predetermined logic state of the timing reference and providing a disable signal for disabling the integrated circuit when the frequency of the input clock signal exceeds the predetermined frequency, wherein the charging and discharging occur repeatedly to generate a stable frequency at the output of the comparison circuit, upon which the timing reference is based.

Claim 14

An apparatus for disabling the operation of an integrated circuit operating under control of an input clock signal, said apparatus comprising: frequency reference generation means for generating a frequency reference having a frequency that is substantially constant with temperature, wherein the frequency reference generation means generates the frequency reference using a bandgap voltage reference and a constant current reference; and comparing means coupled to receive the frequency reference and the input clock signal for comparing a predetermined frequency to the input clock signal during a predetermined logic state of the frequency reference and for providing a disable signal for disabling the integrated circuit when the frequency of the input clock signal exceeds the predetermined frequency.

Claim 15

An apparatus for disabling the operation of an integrated circuit operating under control of an input clock signal, said apparatus comprising: frequency reference generation means for generating a frequency reference having a frequency that is substantially constant with temperature, wherein the frequency reference generation means generates the frequency reference using a bandgap voltage reference and a constant current reference; and comparing means coupled to receive the frequency reference and the input clock signal for comparing a predetermined frequency to the input clock signal during a predetermined logic state of the frequency reference and for providing a disable signal for disabling the integrated circuit when the frequency of the input clock signal exceeds the predetermined frequency.

Claim 25

A method for limiting operating speed of an integrated circuit (IC) clocked by an input clock signal, said method comprising the steps of: generating a frequency reference, wherein the step of generating the frequency reference comprises repeatedly; obtaining a voltage ramp by sourcing a constant current to a gate capacitor, and terminating the voltage ramp when the voltage ramp reaches a bandgap reference level; comparing a predetermined frequency to the frequency of the input clock signal during a predetermined logic state of the frequency reference; and preventing the IC from operating if the input clock signal frequency is greater than the predetermined frequency.

Claim 26

A method for limiting operating speed of an integrated circuit (IC) clocked by an input clock signal, said method comprising the steps of: generating a frequency reference, wherein the step of generating the frequency reference comprises repeatedly; obtaining a voltage ramp by sourcing a constant current to a gate capacitor, and terminating the voltage ramp when the voltage ramp reaches a bandgap reference level; comparing a predetermined frequency to the frequency of the input clock signal during a predetermined logic state of the frequency reference; and preventing the IC from operating if the input clock signal frequency is greater than the predetermined frequency.

Claim 28

An apparatus for disabling the operation of an integrated circuit operating under control of an input clock signal, said apparatus comprising: a timing reference generator generating a timing reference having a frequency that is substantially constant with temperature, wherein the timing reference generator comprises a capacitor; a constant current source coupled to charge the capacitor, wherein the constant current source comprises a constant current reference to generate a current to charge the capacitor to generate a first potential; a bandgap voltage reference generating a second potential, wherein the second potential is non-zero; a comparator coupled to compare the first potential and the second potential to produce an output, wherein the output is in a first state while the second potential exceeds the first potential and flips to a second state when the first potential exceeds the second potential; a discharge mechanism coupled to the capacitor and responsive to the output of the comparator to discharge the capacitor when the output is in the second state causing the first potential received by the comparator to be pulled to ground, such that the output flips back to the first state; wherein the charging and discharging occur repeatedly, such that the output of the comparator comprises a frequency reference signal that has a stable frequency that is independent of temperature and acts as the timing reference; and a comparison circuit coupled to receive the timing reference and the input clock signal comparing a predetermined frequency to the input clock signal during a predetermined logic state of the timing reference and providing a disable signal for disabling the integrated circuit when the frequency of the input clock signal exceeds the predetermined frequency.

Claim 29

An apparatus for disabling the operation of an integrated circuit operating under control of an input clock signal, said apparatus comprising: a timing reference generator generating a timing reference having a frequency that is substantially constant with temperature, wherein the timing reference generator comprises a capacitor; a constant current source coupled to charge the capacitor, wherein the constant current source comprises a constant current reference to generate a current to charge the capacitor to generate a first potential; a bandgap voltage reference generating a second potential, wherein the second potential is non-zero; a comparator coupled to compare the first potential and the second potential to produce an output, wherein the output is in a first state while the second potential exceeds the first potential and flips to a second state when the first potential exceeds the second potential; a discharge mechanism coupled to the capacitor and responsive to the output of the comparator to discharge the capacitor when the output is in the second state causing the first potential received by the comparator to be pulled to ground, such that the output flips back to the first state; wherein the charging and discharging occur repeatedly, such that the output of the comparator comprises a frequency reference signal that has a stable frequency that is independent of temperature and acts as the timing reference; and a comparison circuit coupled to receive the timing reference and the input clock signal comparing a predetermined frequency to the input clock signal during a predetermined logic state of the timing reference and providing a disable signal for disabling the integrated circuit when the frequency of the input clock signal exceeds the predetermined frequency.

Claim 34

An apparatus for limiting the speed of an integrated circuit (IC) externally clocked by an input clock signal, said apparatus comprising: a frequency reference generator, located on the integrated circuit, generating a frequency reference signal that is substantially independent of temperature and process variations on the integrated circuit, wherein the frequency reference generator generates the frequency reference using a bandgap voltage reference and a constant current reference; a counter, located on the integrated circuit, coupled to receive the frequency reference signal and the input clock signal to count clock cycles of the input clock signal that occurs during a period of the frequency reference signal; a storage device, located on the integrated circuit, providing a predetermined value; a comparator, located on the integrated circuit, coupled to receive and compare the count and the predetermined value to generate an output signal, wherein the output signal is at a first state when the count exceeds the predetermined value; and a disable signal generator, located on the integrated circuit, to generate a disable signal in response to the output signal being at the first state to prevent the IC from operating.

Claim 35

An apparatus for limiting the speed of an integrated circuit (IC) externally clocked by an input clock signal, said apparatus comprising: a frequency reference generator, located on the integrated circuit, generating a frequency reference signal that is substantially independent of temperature and process variations on the integrated circuit, wherein the frequency reference generator generates the frequency reference using a bandgap voltage reference and a constant current reference; a counter, located on the integrated circuit, coupled to receive the frequency reference signal and the input clock signal to count clock cycles of the input clock signal that occurs during a period of the frequency reference signal; a storage device, located on the integrated circuit, providing a predetermined value; a comparator, located on the integrated circuit, coupled to receive and compare the count and the predetermined value to generate an output signal, wherein the output signal is at a first state when the count exceeds the predetermined value; and a disable signal generator, located on the integrated circuit, to generate a disable signal in response to the output signal being at the first state to prevent the IC from operating.

Claim 43

An apparatus for disabling the operation of an integrated circuit operating under control of an input clock signal, said apparatus comprising: a timing reference generator generating an internally generated reference signal having a frequency that is substantially independent of temperature, wherein the timing reference generator generates the internally generated reference signal using a bandgap voltage reference and a constant current reference; and a comparison circuit coupled to receive the internally generated reference signal and the input clock signal to compare a predetermined frequency to the input clock signal using the internally generated reference signal as a timing reference, wherein the comparison circuit further provides a disable signal for disabling the integrated circuit when the frequency of the input clock signal exceeds the predetermined frequency.

Claim 44

An apparatus for disabling the operation of an integrated circuit operating under control of an input clock signal, said apparatus comprising: a timing reference generator generating an internally generated reference signal having a frequency that is substantially independent of temperature, wherein the timing reference generator generates the internally generated reference signal using a bandgap voltage reference and a constant current reference; and a comparison circuit coupled to receive the internally generated reference signal and the input clock signal to compare a predetermined frequency to the input clock signal using the internally generated reference signal as a timing reference, wherein the comparison circuit further provides a disable signal for disabling the integrated circuit when the frequency of the input clock signal exceeds the predetermined frequency.