Digital timing discriminator

Claim 2

An integrated frequency discriminator circuit for detecting the frequency of a data input signal about a predetermined frequency threshold, comprising: a first flipflop circuit having a data input, a clock input, a reset input and an output, said data input being coupled for receiving a first logic signal, said clock input being coupled for receiving the data input signal, said output being coupled to said reset input of said first flipflop circuit for providing a first reset signal; a first counter having a clock input, a reset input and an output, said clock input being coupled for receiving a reference signal for adjusting a first count value, said reset input being coupled for receiving said first reset signal for resetting said first count value; a first decode circuit having an input coupled to said output of said first counter and having an output for providing an output signal having said first state while said first count value is equal to a predetermined count threshold and a second state when said first count value is not equal to said predetermined count threshold; a second flipflop circuit having a data input, a clock input, a reset input and an output, said data input being coupled for receiving said first logic signal, said clock input being coupled for receiving the data input signal, said reset input being coupled for receiving said output signal of said first decode circuit; and a third flipflop circuit having a data input, a clock input and an output, said data input being coupled to said output of said second flipflop circuit, said clock input being coupled for receiving the data input signal, said output providing an output signal having said first state when said first count value is reset before reaching said predetermined count threshold and having said second state when said first count value reaches said predetermined count threshold.

Claim 3

The integrated frequency discriminator circuit of claim 1 further comprising: a frequency divider circuit having an input coupled for receiving the data input signal and having an output coupled to said clock input of said first flipflop circuit; an inverter circuit having an input coupled to said output of frequency divider circuit and having an output; and a fourth flipflop circuit having a data input, a clock input, a reset input and an output, said data input being coupled for receiving said first logic signal, said clock input being coupled to said output of said inverter circuit, said output being coupled to said reset input of said fourth flipflop circuit for providing a second reset signal.

Claim 4

The integrated frequency discriminator circuit of claim 2 further comprising: a second counter having a clock input, a reset input and an output, said clock input being coupled for receiving said reference signal, said reset input being coupled for receiving said second reset signal; a second decode circuit having an input coupled to said output of said second counter and having an output; and a logic circuit having first and second inputs and an output, said first input being coupled to said output of said first decode circuit for providing an output signal at the occurrence of said first state of said output signal from said first decode circuit, said second input being coupled to said output of said second decode circuit for providing an output signal at the occurrence of said first state of said output signal from said second decode circuit, said output being coupled to said reset input of said second flipflop circuit.

Claim 5

A circuit, comprising: first means coupled for receiving a data input signal and providing first and second reset signals at first and second outputs respectively in response to said data input signal, said first and second reset signals having a predetermined phase relationship, said first means including, (a) a frequency divider circuit having an input coupled for receiving said data input signal and having an output, (b) a first flipflop circuit having a data input, a clock input, a reset input and an output, said data input being coupled for receiving a first logic signal, said clock input being coupled to said output of said frequency divider circuit, said output being coupled to said reset input of said first flipflop circuit for providing said first reset signal of said first means, (c) an inverter circuit having an input coupled to said output of frequency divider circuit and having an output, and (d) a second flipflop circuit having a data input, a clock input, a reset input and an output, said data input being coupled for receiving said first logic signal, said clock input being coupled to said output of said inverter circuit, said output being coupled to said reset input of said second flipflop circuit for providing said second reset signal of said first means; a first counter having a clock input, a reset input and an output, said clock input being coupled for receiving a reference clock signal for counting a first count value, said reset input receiving said first reset signal for resetting said first count value to a predetermined initial value; a second counter having a clock input, a reset input and an output, said clock input being coupled for receiving said reference clock signal for counting a second count value, said reset input receiving said second reset signal for resetting said second count value to a predetermined initial value; a first decode circuit having an input coupled to said output of said first counter and having an output for providing a first output signal having a first state when said first count value is equal to a predetermined count threshold and a second state when said first count value is not equal to said predetermined count threshold; a second decode circuit having an input coupled to said output of said second counter and having an output for providing a second output signal having a first state when said second count value is equal to said predetermined count threshold and a second state when said second count value is not equal to said predetermined count threshold; and a logic circuit having first and second inputs and an output, said first input being coupled to said output of said first decode circuit for providing an output signal at the occurrence of said first state of said first output signal from said first decode circuit, said second input being coupled to said output of said second decode circuit for providing an output signal at the occurrence of said first state of said second output signal from said second decode circuit.

Claim 6

A circuit, comprising: first means coupled for receiving a data input signal and providing first and second reset signals at first and second outputs respectively in response to said data input signal, said first and second reset signals having a predetermined phase relationship, said first means including, (a) a frequency divider circuit having an input coupled for receiving said data input signal and having an output, (b) a first flipflop circuit having a data input, a clock input, a reset input and an output, said data input being coupled for receiving a first logic signal, said clock input being coupled to said output of said frequency divider circuit, said output being coupled to said reset input of said first flipflop circuit for providing said first reset signal of said first means, (c) an inverter circuit having an input coupled to said output of frequency divider circuit and having an output, and (d) a second flipflop circuit having a data input, a clock input, a reset input and an output, said data input being coupled for receiving said first logic signal, said clock input being coupled to said output of said inverter circuit, said output being coupled to said reset input of said second flipflop circuit for providing said second reset signal of said first means; a first counter having a clock input, a reset input and an output, said clock input being coupled for receiving a reference clock signal for counting a first count value, said reset input receiving said first reset signal for resetting said first count value to a predetermined initial value; a second counter having a clock input, a reset input and an output, said clock input being coupled for receiving said reference clock signal for counting a second count value, said reset input receiving said second reset signal for resetting said second count value to a predetermined initial value; a first decode circuit having an input coupled to said output of said first counter and having an output for providing a first output signal having a first state when said first count value is equal to a predetermined count threshold and a second state when said first count value is not equal to said predetermined count threshold; a second decode circuit having an input coupled to said output of said second counter and having an output for providing a second output signal having a first state when said second count value is equal to said predetermined count threshold and a second state when said second count value is not equal to said predetermined count threshold; and a logic circuit having first and second inputs and an output, said first input being coupled to said output of said first decode circuit for providing an output signal at the occurrence of said first state of said first output signal from said first decode circuit, said second input being coupled to said output of said second decode circuit for providing an output signal at the occurrence of said first state of said second output signal from said second decode circuit.

Claim 7

A circuit, comprising: first means coupled for receiving a data input signal and providing first and second reset signals at first and second outputs respectively in response to said data input signal, said first and second reset signals having a predetermined phase relationship; a first counter having a clock input, a reset input and an output, said clock input being coupled for receiving a reference clock signal for counting a first count value, said reset input receiving said first reset signal for resetting said first count value to a predetermined initial value; a second counter having a clock input, a reset input and an output, said clock input being coupled for receiving said reference clock signal for counting a second count value, said reset input receiving said second reset signal for resetting said second count value to a predetermined initial value; a first decode circuit having an input coupled to said output of said first counter and having an output for providing a first output signal having a first state when said first count value is equal to a predetermined count threshold and a second state when said first count value is not equal to said predetermined count threshold; a second decode circuit having an input coupled to said output of said second counter and having an output for providing a second output signal having a first state when said second count value is equal to said predetermined count threshold and a second state when said second count value is not equal to said predetermined count threshold; a logic circuit having first and second inputs and an output, said first input being coupled to said output of said first decode circuit for providing an output signal at the occurrence of said first state of said first output signal from said first decode circuit, said second input being coupled to said output of said second decode circuit for providing an output signal at the occurrence of said first state of said second output signal from said second decode circuit; a delay circuit having an input coupled for receiving said data input signal and having an output; a third flipflop circuit having a data input, a clock input, a reset input and an output, said data input being coupled for receiving said first logic signal, said clock input being coupled to said output of said delay circuit, said reset input being coupled to said output of said logic circuit; and a fourth flipflop circuit having a data input, a clock input and an output, said data input being coupled to said output of said third flipflop circuit, said clock input being coupled to said output of said delay circuit, said output providing an output signal of the circuit having a first state when said first and second count values are reset before reaching said predetermined count threshold and having a second state when said first or second count value reaches said predetermined count threshold.

Claim 8

A circuit, comprising: first means coupled for receiving a data input signal and providing first and second reset signals at first and second outputs respectively in response to said data input signal, said first and second reset signals having a predetermined phase relationship; a first counter having a clock input, a reset input and an output, said clock input being coupled for receiving a reference clock signal for counting a first count value, said reset input receiving said first reset signal for resetting said first count value to a predetermined initial value; a second counter having a clock input, a reset input and an output, said clock input being coupled for receiving said reference clock signal for counting a second count value, said reset input receiving said second reset signal for resetting said second count value to a predetermined initial value; a first decode circuit having an input coupled to said output of said first counter and having an output for providing a first output signal having a first state when said first count value is equal to a predetermined count threshold and a second state when said first count value is not equal to said predetermined count threshold; a second decode circuit having an input coupled to said output of said second counter and having an output for providing a second output signal having a first state when said second count value is equal to said predetermined count threshold and a second state when said second count value is not equal to said predetermined count threshold; a logic circuit having first and second inputs and an output, said first input being coupled to said output of said first decode circuit for providing an output signal at the occurrence of said first state of said first output signal from said first decode circuit, said second input being coupled to said output of said second decode circuit for providing an output signal at the occurrence of said first state of said second output signal from said second decode circuit; a delay circuit having an input coupled for receiving said data input signal and having an output; a third flipflop circuit having a data input, a clock input, a reset input and an output, said data input being coupled for receiving said first logic signal, said clock input being coupled to said output of said delay circuit, said reset input being coupled to said output of said logic circuit; and a fourth flipflop circuit having a data input, a clock input and an output, said data input being coupled to said output of said third flipflop circuit, said clock input being coupled to said output of said delay circuit, said output providing an output signal of the circuit having a first state when said first and second count values are reset before reaching said predetermined count threshold and having a second state when said first or second count value reaches said predetermined count threshold.