Abstract A watchdog timer for monitoring the operation of a computer monitors if the period of a writing signal (W T ) generated by each execution of an instruction of a program is within the predetermined duration. The present watchdog timer comprises a register (2) for storing predetermined DATA upon receipt of the writing signal (W T ), a counter (4) which is incremented by a clock pulse (φ), a comparator (3) for providing coincidence output signal when content of the counter reaches said predetermined DATA in the register (2), a first flip-flop (F 1 ) for storing said coincidence output signal for one period of said clock pulse (φ), a second flip-flop (F 2 ) for storing said coincidence output signal upon receipt of said clock pulse (φ), a third flip-flop (F 3 ) for storing output of said second flip-flop (F 2 ) upon receipt of said clock pulse (φ), an AND circuit (G 1 ) for providing logical product of reverse output (Q 1 ) of said first flip-flop (F 1 ) and said writing signal (W T ), and an OR circuit (G.sub. 2) for receiving an output of said third flip-flop (F 3 ) and an output of said AND circuit (G 1 ) and producing an alarm signal NG which indicates an error of a computer to be monitored.
A watchdog timer comprising; a register (2) for presetting predetermined DATA upon receipt of a writing signal (W T ), a counter (4) which is incremented by a clock pulse (φ), a comparator (3) which compares contents of said register (2) with contents of said counter and providing a coincidence output signal when two contents coincide with each other, a first flip-flop (F 1 ) for storing said coincidence output signal for one period of said clock pulse φ, a second flip-flop (F 2 ) for storing said coincidence output signal upon receipt of said clock pulse φ, a third flip-flop (F 3 ) for storing output of said second flip-flop F 2 upon receipt of said clock pulse φ, an AND circuit (G 1 ) for providing logical product of a reverse output Q 1 of said first flip-flop F 1 and said writing signal(W T ) , and an OR circuit (G 2 ) for receiving an output of said third flip-flop F 3 and an output of said AND circuit (G 1 ) and producing an alarm signal NG which indicates an error of a computer to be monitored.
Claim 2
Dependent Claim
192 words
A watchdog timer comprising; a register (2) for presetting predetermined DATA upon receipt of a writing signal (W T ), a counter (4) which is incremented by a clock pulse (φ), a comparator (3) which compares contents of said register (2) with contents of said counter and providing a coincidence output signal when two contents coincide with each other, a first flip-flop (F 1 ) for storing said coincidence output signal for one period of said clock pulse φ, a second flip-flop (F 2 ) for storing said coincidence output signal upon receipt of said clock pulse φ, a third flip-flop (F 3 ) for storing output of said second flip-flop F 2 upon receipt of said clock pulse φ, an AND circuit (G 1 ) for providing logical product of a reverse output Q 1 of said first flip-flop F 1 and said writing signal(W T ) , and an OR circuit (G 2 ) for receiving an output of said third flip-flop F 3 and an output of said AND circuit (G 1 ) and producing an alarm signal NG which indicates an error of a computer to be monitored.
Claim 3
Dependent Claim
25 words
A watchdog timer according to claim 1 further comprising a start-stop circuit (4') which selectively transmits said clock pulse φ in responce to an instruction.
Claim 4
Dependent Claim
36 words
A watchdog timer according to claim 1 further comprising an OR circuit (G 3 ) which receives said writing signal W T and an output of said second flip-flop F 2 to reset said counter(4) .
Claim 5
Dependent Claim
26 words
A watchdog timer according to claim 1, wherein said flip-flops F 1 and F 3 are set and reset, respectively, by an initial reset signal RES.