Method of manufacturing Si-Ge thin film transistor

Claim 1

A method for making a thin film transistor comprising the steps of: providing a substrate having a surface; depositing a p-doped Si layer on said surface; patterning said p-doped Si layer to remove portions of said Si layer and to define a source region, a drain region and a channel region; depositing a SiGe layer containing about 80 atomic % Ge by CVD using a mixed gas of SiH 4 and GeH 4 at a flow rate of GeH 4 /(GeH 4 +SiH 4 ) of from about 0.3 to about 0.4; patterning said SiGe layer and etching back so that only a portion of said SiGe layer remains in said channel region; annealing said source, drain and channel regions by irradiation with an XeCl laser to crystallize the source, drain and channel regions; depositing an insulation layer over said source, drain and channel regions; patterning and etching the insulator layer to form a hole for said source and drain regions, respectively; forming source and drain electrodes in the respective holes for said source and drain regions; forming a gate electrode above said channel region by depositing a SiGe layer by CVD and patterning and etching the SiGe layer to provide said gate electrode, whereby a thin film transistor having a carrier mobility at 300° K of 1400 cm 2 /Volt second or higher and a ratio of on-current to off-current from about 10 6 to about 10 7 is provided.

Claim 2

A method for making a thin film transistor comprising the steps of: providing a substrate having a surface; depositing a p-doped Si layer on said surface; patterning said p-doped Si layer to remove portions of said Si layer and to define a source region, a drain region and a channel region; depositing a SiGe layer containing about 80 atomic % Ge by CVD using a mixed gas of SiH 4 and GeH 4 at a flow rate of GeH 4 /(GeH 4 +SiH 4 ) of from about 0.3 to about 0.4; patterning said SiGe layer and etching back so that only a portion of said SiGe layer remains in said channel region; annealing said source, drain and channel regions by irradiation with an XeCl laser to crystallize the source, drain and channel regions; depositing an insulation layer over said source, drain and channel regions; patterning and etching the insulator layer to form a hole for said source and drain regions, respectively; forming source and drain electrodes in the respective holes for said source and drain regions; forming a gate electrode above said channel region by depositing a SiGe layer by CVD and patterning and etching the SiGe layer to provide said gate electrode, whereby a thin film transistor having a carrier mobility at 300° K of 1400 cm 2 /Volt second or higher and a ratio of on-current to off-current from about 10 6 to about 10 7 is provided.