Patent US5590293A successfully refreshed from Google Patents.
US5590293A
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Dynamic microbranching with programmable hold on condition, to programmable dynamic microbranching delay minimization
Assignee: Samsung Electronics Co Ltd
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Filing: 1995-04-18
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Granted: 1996-12-31
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Expires: 2015-04-18
Abstract
Abstract A pipelined, microcoded CPU employs conditional branching in microcode execution Data path conditions produced by one microinstruction are used in the selection of a following microinstruction. In high-performance systems, multiple cycle microbranch latency requires that the generation of microbranch conditions be pipelined. Usually a microbranch condition is used exactly once, at the earliest possible time, when dynamic microbranch conditions are only valid a fixed number of microinstructions later in the pipeline. Flexibility of the microcode algorithm is increased by selectively inhibiting the update of the dynamic conditions to delay the use of the condition by one or more cycles, under microcode control, thereby implementing dynamic microbranches, while allowing use of previous dynamic microbranch state.
Inventors
- 👤 George M. Uhler
- 👤 George G. Mills
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 09:15
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/22; G06F9/26; G06F9/262; G06F9/264; G06F9/28
Claims Analysis
Total Claims: 28
Claim 1
Independent Claim
210 words
A processor comprising: a) a control store for producing microinstructions in response to microaddresses applied to an input of the control store, the processor operating in machine cycles and the control store producing one of said microinstructions each machine cycle; each microinstruction executing during a plurality of successive machine cycles; b) a plurality of execution stages, each execution stage using each one of said microinstructions in said successive machine cycles whereby execution of each of said microinstructions overlaps execution of other of said microinstructions, with latch means in each of said execution stages receiving said microinstructions to store and shift each microinstruction for said successive machine cycles; c) means for generating condition information in response to a condition at an output of one of said execution stages in each of said successive machine cycles; d) means for generating a next microaddress using said condition information, and for applying said next microaddress to said input of the control store; e) and means for selecting said condition information generated in a selected machine cycle, for use by said means for generating a next micro-address after a designated number of said successive machine cycles, said designated number of said successive machine cycles being dependent upon a decoded field of one of said microinstructions.
Claim 2
Dependent Claim
210 words
A processor comprising: a) a control store for producing microinstructions in response to microaddresses applied to an input of the control store, the processor operating in machine cycles and the control store producing one of said microinstructions each machine cycle; each microinstruction executing during a plurality of successive machine cycles; b) a plurality of execution stages, each execution stage using each one of said microinstructions in said successive machine cycles whereby execution of each of said microinstructions overlaps execution of other of said microinstructions, with latch means in each of said execution stages receiving said microinstructions to store and shift each microinstruction for said successive machine cycles; c) means for generating condition information in response to a condition at an output of one of said execution stages in each of said successive machine cycles; d) means for generating a next microaddress using said condition information, and for applying said next microaddress to said input of the control store; e) and means for selecting said condition information generated in a selected machine cycle, for use by said means for generating a next micro-address after a designated number of said successive machine cycles, said designated number of said successive machine cycles being dependent upon a decoded field of one of said microinstructions.
Claim 3
Dependent Claim
29 words
A processor according to claim 1 wherein said processor includes an ALU in one of said execution stages and said condition is detected at the output of the ALU.
Claim 4
Dependent Claim
23 words
A processor according to claim 1 wherein said condition is detected at an output of a second of said plurality of execution stages.
Claim 5
Dependent Claim
16 words
A processor according to claim 3 wherein there are at least three of said execution stages.
Claim 6
Dependent Claim
53 words
A processor according to claim 1 wherein said microaddress for a given one of said microinstructions is produced during a first of said successive machine cycles, and said condition is detected during a later one of said successive machine cycles while said given one of the microinstructions is stored in said latch means.
Claim 7
Dependent Claim
30 words
A processor according to claim 5 wherein said later one of said machine cycles is more than two successive machine cycles later than said first of said successive machine cycles.
Claim 8
Dependent Claim
25 words
A processor according to claim 5 wherein said using of said condition is inhibited for at least one machine cycle by said means for selecting.
Claim 9
Dependent Claim
189 words
A processor comprising: a) a code store for producing instruction code in response to addresses applied to an input of the code store, the processor operating in repetitive machine cycles and the code store producing one of said instruction codes each machine cycle; each one of said instruction codes executing during a plurality of successive machine cycles; b) a plurality of execution stages, each one of said execution stages using each said instruction code in said successive machine cycles whereby execution of each of said instruction codes overlaps execution of other of said instruction codes, with latch means in each of said execution stages receiving said instruction codes to store each instruction code for at least one of said plurality of successive machine cycles; c) means for generating condition information in response to a condition at an output of one of said execution stages; d) means for generating a next address in using said condition information and applying said next address to said input of the code store; e) and means for inhibiting said using of said condition information in response to a decoded field of said instruction code.
Claim 10
Dependent Claim
189 words
A processor comprising: a) a code store for producing instruction code in response to addresses applied to an input of the code store, the processor operating in repetitive machine cycles and the code store producing one of said instruction codes each machine cycle; each one of said instruction codes executing during a plurality of successive machine cycles; b) a plurality of execution stages, each one of said execution stages using each said instruction code in said successive machine cycles whereby execution of each of said instruction codes overlaps execution of other of said instruction codes, with latch means in each of said execution stages receiving said instruction codes to store each instruction code for at least one of said plurality of successive machine cycles; c) means for generating condition information in response to a condition at an output of one of said execution stages; d) means for generating a next address in using said condition information and applying said next address to said input of the code store; e) and means for inhibiting said using of said condition information in response to a decoded field of said instruction code.
Claim 11
Dependent Claim
35 words
A processor according to claim 8 wherein said processor includes an arithmetic & logic unit in one of said execution stages and said condition is detected at the output of said arithmetic & logic unit.
Claim 12
Dependent Claim
25 words
A processor according to claim 8 wherein said condition is detected at an output of an execution stage after the first of said execution stages.
Claim 13
Dependent Claim
31 words
A processor according to claim 10 wherein there are at least three of said execution stages, and said condition is detected at the output of the second of such execution stages.
Claim 14
Dependent Claim
55 words
A processor according to claim 8 wherein said address for a given one of said instruction codes is produced during a first of said successive machine cycles, and said condition is detected during a later one of said successive machine cycles while said given one of the instruction codes is stored in said latch means.
Claim 15
Dependent Claim
30 words
A processor according to claim 12 wherein said later one of said machine cycles is more than two successive machine cycles later than said first of said successive machine cycles.
Claim 16
Dependent Claim
20 words
A processor according to claim 12 wherein said using of said condition is inhibited for at least one machine cycle.
Claim 17
Dependent Claim
20 words
A processor according to claim 8 wherein said instruction codes are microinstructions, and said code store is a microinstruction store.
Claim 18
Independent Claim
175 words
A method of operating a digital processor comprising the steps of: a) producing instruction code from a code store in response to addresses applied to an input of the code store, the processor operating in repetitive machine cycles and producing one of said instruction codes from the code store in each machine cycle, each one of said instruction codes executing during a plurality of successive machine cycles; b) executing each said instruction code in a plurality of execution stages in said processor in successive machine cycles whereby execution of instruction codes is overlapped, and storing each instruction code for at least one of said plurality of successive machine cycles; c) detecting a condition at an output of one of said execution stages to produce condition information in each of said successive machine cycle; d) generating a next address using said condition information and applying said next address to said input of the code store; e) and inhibiting said using of said condition information in response to the content of a part of said instruction code.
Claim 19
Independent Claim
175 words
A method of operating a digital processor comprising the steps of: a) producing instruction code from a code store in response to addresses applied to an input of the code store, the processor operating in repetitive machine cycles and producing one of said instruction codes from the code store in each machine cycle, each one of said instruction codes executing during a plurality of successive machine cycles; b) executing each said instruction code in a plurality of execution stages in said processor in successive machine cycles whereby execution of instruction codes is overlapped, and storing each instruction code for at least one of said plurality of successive machine cycles; c) detecting a condition at an output of one of said execution stages to produce condition information in each of said successive machine cycle; d) generating a next address using said condition information and applying said next address to said input of the code store; e) and inhibiting said using of said condition information in response to the content of a part of said instruction code.
Claim 20
Dependent Claim
29 words
A method according to claim 16 wherein said processor includes an arithmetic & logic unit and said condition is detected at an output of said arithmetic & logic unit.
Claim 21
Dependent Claim
25 words
A method according to claim 16 wherein said condition is detected at an output of an execution stage after the first of said execution stages.
Claim 22
Dependent Claim
31 words
A method according to claim 18 wherein there are at least three of said execution stages, and said condition is detected at the output of the second of such execution stages.
Claim 23
Dependent Claim
51 words
A method according to claim 16 wherein said address for a given one of said instruction codes is produced during a first of said successive machine cycles, and said condition is detected during a later one of said successive machine cycles while said given one of the instruction codes is stored.
Claim 24
Dependent Claim
28 words
A method according to claim 20 wherein said later one of said machine cycles is more than two successive machine cycles later than said first successive machine cycle.
Claim 25
Dependent Claim
20 words
A method according to claim 20 wherein said using of said condition is inhibited for at least one machine cycle.
Claim 26
Dependent Claim
20 words
A method according to claim 16 wherein said instruction codes are microinstructions, and said code store is a microinstruction store.
Claim 27
Independent Claim
161 words
A method of addressing a memory to produce control codes for controlling a plurality of successive stages operating in response to said control codes, wherein said memory produces a set of control codes during each of successive cycle times, and each said set of control codes is latched for use in said successive stages in successive ones of said cycle times, wherein said memory is a control store and said control codes are microinstructions, comprising the steps of: a) generating a next address for said memory in response to a condition produced from one of said stages; b) and, in response to a part of one of said control codes representing a conditional branching condition, generating a control signal for inhibiting said step of generating a next address in response to a condition produced from one of said stages, said step of inhibiting being in addition to an inhibit resulting from time delay in said step of generating a next address.
Claim 28
Independent Claim
161 words
A method of addressing a memory to produce control codes for controlling a plurality of successive stages operating in response to said control codes, wherein said memory produces a set of control codes during each of successive cycle times, and each said set of control codes is latched for use in said successive stages in successive ones of said cycle times, wherein said memory is a control store and said control codes are microinstructions, comprising the steps of: a) generating a next address for said memory in response to a condition produced from one of said stages; b) and, in response to a part of one of said control codes representing a conditional branching condition, generating a control signal for inhibiting said step of generating a next address in response to a condition produced from one of said stages, said step of inhibiting being in addition to an inhibit resulting from time delay in said step of generating a next address.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-12-31 | 2000-07-01 | 2000-12-31 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-12-31 | 2004-07-01 | 2004-12-31 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-12-31 | 2008-07-01 | 2008-12-31 | $7700.00 | Window Closed / Lapsed |