US4701842A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method and apparatus for avoiding excessive delay in a pipelined processor during the execution of a microbranch instruction
Assignee: International Business Machines Corp
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Filing: 1985-10-04
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Granted: 1987-10-20
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Expires: 2005-10-04
Abstract
Abstract In a pipelined instruction execution system including a microstore for storing sequences of microinstruction addresses associated with each macroinstruction, a nanostore for randomly storing unique microinstructions, and an execution unit for executing the microinstructions, a no-op/prefetch apparatus, according to the present invention, prevents a microinstruction address, stored in the microstore, from accessing the nanostore and forces a no-op address into the nanostore when the execution unit executes a conditional microbranch instruction. A no-op microinstruction, corresponding to the no-op address, is retrieved from the nanostore and is executed in the execution unit. During the execution of the no-op microinstruction in the execution unit, the no-op/prefetch apparatus permits either the next sequential microinstruction address following the conditional microbranch instruction to access the nanostore or another non-sequential microinstruction address to access the nanostore, the selection of the next sequential microinstruction address or said another non-sequential microinstruction depending upon the outcome of the execution of the conditional microbranch instruction by the execution unit. As a result, when the microstore and the nanostore are utilized, only one cycle of delay, for resolution of the pipeline, will be encountered following the execution of the conditional branch microinstruction by the execution unit. Furthermore, additional real estate is available on the integrated circuit chip on which the instruction execution system is disposed.
Inventors
- 👤 Howard T. Olnowich
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 20:35
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/22; G06F9/28; G06F9/26; G06F9/262; G06F9/264; G06F9/265
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
149 words
A pipelined instruction execution system, comprising: first store means for storing sets of sequential addresses; second store means connected to said first store means for storing a plurality of microinstructions and a no-op microinstruction, each microinstruction corresponding to an address stored in said first store means; execution means connected to the second store means for executing a set of microinstructions stored in said second store means in a sequential fashion in accordance with the addresses stored in said first store means and for executing said no-op microinstruction; and first means interconnected between the first and second store means for preventing a microinstruction address from said first store means from accessing said second store means for the purpose of searching for a microinstruction stored therein and for accessing said second store means with an address indicative of said no-op microinstruction when said execution means is executing a conditional branch microinstruction.
Claim 2
Dependent Claim
149 words
A pipelined instruction execution system, comprising: first store means for storing sets of sequential addresses; second store means connected to said first store means for storing a plurality of microinstructions and a no-op microinstruction, each microinstruction corresponding to an address stored in said first store means; execution means connected to the second store means for executing a set of microinstructions stored in said second store means in a sequential fashion in accordance with the addresses stored in said first store means and for executing said no-op microinstruction; and first means interconnected between the first and second store means for preventing a microinstruction address from said first store means from accessing said second store means for the purpose of searching for a microinstruction stored therein and for accessing said second store means with an address indicative of said no-op microinstruction when said execution means is executing a conditional branch microinstruction.
Claim 3
Dependent Claim
93 words
The pipelined instruction execution system of claim 1, wherein said first means permits either a first microinstruction address or a second microinstruction address to access said second store means during the execution of said no-op microinstruction by said execution means, the selection of said first or second microinstruction address for accessing said second store means depending upon the results of the execution of said conditional branch microinstruction by said execution means, said first microinstruction address representing the next sequential microinstruction following said conditional branch microinstruction, said second microinstruction address representing another non-sequential microinstruction.
Claim 4
Dependent Claim
104 words
The pipelined instruction execution system of claim 2, wherein said first means comprises: control means connected to said execution means for developing a select signal when said execution means is executing said conditional branch microinstruction; and multiplexer means having an output connected to said second store means and responsive to a first signal representing said address indicative of said no-op instruction, to a second signal representing said microinstruction address from said first store means and to said select signal for selecting said first signal in response to said select signal from said control means thereby permitting said execution means to execute said no-op instruction.
Claim 5
Dependent Claim
83 words
The pipelined instruction execution system of claim 3, wherein said control means develops an inhibit load signal during the execution of said no-op instruction by said execution means when said results of the execution of said conditional branch microinstruction by said execution means indicated that said second microinstruction address shall access said second store means, said inhibit load signal preventing said first microinstruction address from accessing said seond store means thereby allowing said second microinstruction address to subsequently access said second store means.
Claim 6
Dependent Claim
81 words
The pipelined instruction execution system of claim 4, further comprising: output register means interconnected between said first store means and said multiplexer means and responsive to said inhibit load signal for preventing said first microinstruction address from being loaded therein in response to said inhibit load signal and for allowing said second microinstruction address to be loaded therein in response to the absence of said inhibit load signal thereby allowing said second microinstruction address to subsequently access said second store means.
Claim 7
Independent Claim
147 words
A method of pipelining in a pipelined instruction execution system including a first store means for storing sets of sequential addresses, a second store means connected to the first store means for storing microinstructions corresponding to said addresses and a no-op microinstruction and an execution means connected to the second store means for executing the microinstructions, comprising the steps of: forcing a no-op microinstruction address corresponding to said no-op microinstruction to access said second store means when said execution means is executing a conditional branch microinstruction; and preventing a first microinstruction address, representing a next sequential microinstruction folowing said conditional branch microinstruction, from accessing said second store means during the execution of said no-op instruction by said execution means when a previous result of the execution of said conditional branch microinstruction indicated that a second microinstruction address, representing another non-sequential microinstruction, should access said second store means.
Claim 8
Independent Claim
147 words
A method of pipelining in a pipelined instruction execution system including a first store means for storing sets of sequential addresses, a second store means connected to the first store means for storing microinstructions corresponding to said addresses and a no-op microinstruction and an execution means connected to the second store means for executing the microinstructions, comprising the steps of: forcing a no-op microinstruction address corresponding to said no-op microinstruction to access said second store means when said execution means is executing a conditional branch microinstruction; and preventing a first microinstruction address, representing a next sequential microinstruction folowing said conditional branch microinstruction, from accessing said second store means during the execution of said no-op instruction by said execution means when a previous result of the execution of said conditional branch microinstruction indicated that a second microinstruction address, representing another non-sequential microinstruction, should access said second store means.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 1990-10-19 | 1991-04-20 | 1991-10-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-10-19 | 1995-04-20 | 1995-10-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-10-19 | 1999-04-20 | 1999-10-20 | $7700.00 | Window Closed / Lapsed |