Process for fabricating a non-silicided region in an integrated circuit

Claim 2

A process for fabricating a non-silicided region in an integrated circuit comprising the steps of: providing a substrate having a silicide blocking layer overlying a dielectric layer; forming a carbonaceous mask on a first portion of the silicide blocking layer and leaving a second portion exposed; partially etching the second portion of the silicide blocking layer using the carbonaceous mask as an etching mask; removing the carbonaceous mask; etching away the second portion of the silicide blocking layer, after removing the carbonaceous mask, to expose a portion of the dielectric layer; etching away the portion of the dielectric layer; and forming a silicide layer in the portion of the substrate, after etching away the portion of the dielectric layer.

Claim 3

The process of claim 1, wherein the steps of partially etching and etching comprise reactive ion etching using a non-carbonaceous gaseous mixture.

Claim 4

The process of claim 1, wherein the step of forming a carbonaceous mask comprises forming a patterned layer of photoresist on the silicide blocking layer.

Claim 5

The process of claim 1, wherein the step of providing a silicide blocking layer comprises depositing a layer of silicon nitride.

Claim 6

A process for fabricating a non-silicided region in an integrated circuit comprising the steps of: providing a substrate having a first region adjacent to a second region, and a junction intermediate to the first and second regions; forming a silicide blocking layer overlying the substrate; forming a carbonaceous mask on a first portion of the silicide blocking layer overlying the junction and a portion of the first and second regions adjacent to the junction, and leaving a second portion of the silicide blocking layer exposed; partially etching the second portion of the silicide blocking layer using the carbonaceous mask as an etching mask; removing the carbonaceous mask; etching away the second portion of the silicide blocking layer, after removing the carbonaceous mask, to expose a portion of the first and second regions; and forming a silicide layer in the portion of the substrate, after etching away the second portion of the silicide blocking layer.

Claim 7

A process for fabricating a non-silicided region in an integrated circuit comprising the steps of: providing a substrate having a first region adjacent to a second region, and a junction intermediate to the first and second regions; forming a silicide blocking layer overlying the substrate; forming a carbonaceous mask on a first portion of the silicide blocking layer overlying the junction and a portion of the first and second regions adjacent to the junction, and leaving a second portion of the silicide blocking layer exposed; partially etching the second portion of the silicide blocking layer using the carbonaceous mask as an etching mask; removing the carbonaceous mask; etching away the second portion of the silicide blocking layer, after removing the carbonaceous mask, to expose a portion of the first and second regions; and forming a silicide layer in the portion of the substrate, after etching away the second portion of the silicide blocking layer.

Claim 8

The process of claim 5, wherein the step of forming a carbonaceous mask comprises forming a patterned layer of photoresist on the silicide blocking layer.

Claim 9

The process of claim 6, wherein the steps of partially etching and etching comprise reactive ion etching using a non-carbonaceous gaseous mixture.

Claim 10

The process of claim 7, wherein the step of providing a silicide blocking layer comprises depositing a layer of silicon nitride.

Claim 11

A process for fabricating a non-silicided region in an integrated circuit comprising the steps of: providing a substrate having a surface and having a field oxide region at the substrate surface; forming a field gate electrode overlying a portion of the field oxide region; forming a dielectric layer overlying the field gate electrode and the substrate surface; forming a silicide blocking layer on the dielectric layer; forming a carbonaceous mask on a first portion of the silicide blocking layer, the first portion overlying the field gate electrode, the field oxide region, and a portion of the substrate adjacent to the field oxide region, and leaving a second portion exposed; partially etching the second portion of the silicide blocking layer using the carbonaceous mask as an etching mask; removing the carbonaceous mask; etching away the second portion of the silicide blocking layer, after removing the carbonaceous mask, to expose a portion of the dielectric layer; etching away the portion of the dielectric layer; and forming a silicide layer in the portion of the substrate, after etching away the portion of the dielectric layer.

Claim 12

A process for fabricating a non-silicided region in an integrated circuit comprising the steps of: providing a substrate having a surface and having a field oxide region at the substrate surface; forming a field gate electrode overlying a portion of the field oxide region; forming a dielectric layer overlying the field gate electrode and the substrate surface; forming a silicide blocking layer on the dielectric layer; forming a carbonaceous mask on a first portion of the silicide blocking layer, the first portion overlying the field gate electrode, the field oxide region, and a portion of the substrate adjacent to the field oxide region, and leaving a second portion exposed; partially etching the second portion of the silicide blocking layer using the carbonaceous mask as an etching mask; removing the carbonaceous mask; etching away the second portion of the silicide blocking layer, after removing the carbonaceous mask, to expose a portion of the dielectric layer; etching away the portion of the dielectric layer; and forming a silicide layer in the portion of the substrate, after etching away the portion of the dielectric layer.

Claim 13

The process of claim 9, wherein the steps of partially etching and etching comprise reactive ion etching using a gaseous mixture having fluorinated etching species as one component and oxygen as another component.

Claim 14

The process of claim 9, wherein the step of forming a field gate electrode further comprises forming an MOS gate electrode overlying the substrate surface and spaced away from the field gate electrode.

Claim 15

The process of claim 11, wherein the step of etching away the second portion of the silicide blocking layer further comprises forming sidewall spacers adjacent to the MOS gate electrode.

Claim 16

A process for fabricating a non-silicided region in an integrated circuit comprising the steps of: providing a substrate having a substrate surface and having a field oxide region at the substrate surface; forming a field gate electrode overlying a portion of the field oxide region; forming an MOS gate electrode overlying the substrate surface and spaced away from the field gate electrode; forming a dielectric layer overlying the field gate electrode, the MOS gate electrode, and the substrate surface; forming a silicide blocking layer overlying the dielectric layer; forming a carbonaceous mask on a first portion of the silicide blocking layer, the first portion overlying the MOS gate electrode, the field oxide region, and a portion of the substrate adjacent to the field oxide region, and leaving a second portion exposed; reactive ion etching using a gaseous mixture having fluorinated etching species as one component and oxygen as another component to partially etch the second portion of the silicide blocking layer using the carbonaceous mask as an etching mask; removing the carbonaceous mask; reactive ion etching using the gaseous mixture to etch away the second portion of the silicide blocking layer; forming sidewall spacers adjacent to the MOS gate electrode; removing portions of the dielectric layer exposed by the first portion of the silicide blocking layer and by the sidewall spacers to expose portions of the substrate surface; and forming silicide regions in expose portions of the substrate surface, after removing the portions of the dielectric layer, wherein the first portion of the silicide blocking layer and the sidewall spacers prevent the formation of a silicide regions in the substrate underlying the first portion of the silicide blocking layer and the sidewall spacers.

Claim 17

A process for fabricating a non-silicided region in an integrated circuit comprising the steps of: providing a substrate having a substrate surface and having a field oxide region at the substrate surface; forming a field gate electrode overlying a portion of the field oxide region; forming an MOS gate electrode overlying the substrate surface and spaced away from the field gate electrode; forming a dielectric layer overlying the field gate electrode, the MOS gate electrode, and the substrate surface; forming a silicide blocking layer overlying the dielectric layer; forming a carbonaceous mask on a first portion of the silicide blocking layer, the first portion overlying the MOS gate electrode, the field oxide region, and a portion of the substrate adjacent to the field oxide region, and leaving a second portion exposed; reactive ion etching using a gaseous mixture having fluorinated etching species as one component and oxygen as another component to partially etch the second portion of the silicide blocking layer using the carbonaceous mask as an etching mask; removing the carbonaceous mask; reactive ion etching using the gaseous mixture to etch away the second portion of the silicide blocking layer; forming sidewall spacers adjacent to the MOS gate electrode; removing portions of the dielectric layer exposed by the first portion of the silicide blocking layer and by the sidewall spacers to expose portions of the substrate surface; and forming silicide regions in expose portions of the substrate surface, after removing the portions of the dielectric layer, wherein the first portion of the silicide blocking layer and the sidewall spacers prevent the formation of a silicide regions in the substrate underlying the first portion of the silicide blocking layer and the sidewall spacers.

Claim 18

A process for fabricating a non-silicided region in an integrated circuit comprising the steps of: providing a substrate containing an electrostatic discharge protection transistor, the electrostatic discharge protection transistor including a gate electrode and a source region and a drain region on opposite sides of the gate electrode; forming a silicide blocking layer to overlie the electrostatic discharge protection transistor; forming a carbonaceous mask on a first portion of the silicide blocking layer overlying the gate electrode and a portion of the source and drain regions adjacent to the gate electrode, and leaving a second portion of the silicide blocking layer exposed; partially etching the second portion of the silicide blocking layer using the carbonaceous mask as an etching mask; removing the carbonaceous mask; etching away the second portion of the silicide blocking layer, after removing the carbonaceous mask, to expose a portion of the substrate; and forming a silicide layer in the portion of the substrate, after etching away the second portion of the silicide blocking layer.

Claim 19

A process for fabricating a non-silicided region in an integrated circuit comprising the steps of: providing a substrate containing an electrostatic discharge protection transistor, the electrostatic discharge protection transistor including a gate electrode and a source region and a drain region on opposite sides of the gate electrode; forming a silicide blocking layer to overlie the electrostatic discharge protection transistor; forming a carbonaceous mask on a first portion of the silicide blocking layer overlying the gate electrode and a portion of the source and drain regions adjacent to the gate electrode, and leaving a second portion of the silicide blocking layer exposed; partially etching the second portion of the silicide blocking layer using the carbonaceous mask as an etching mask; removing the carbonaceous mask; etching away the second portion of the silicide blocking layer, after removing the carbonaceous mask, to expose a portion of the substrate; and forming a silicide layer in the portion of the substrate, after etching away the second portion of the silicide blocking layer.

Claim 20

The process of claim 14, wherein the steps of partially etching and etching comprise reactive ion etching using a gaseous mixture including fluorinated etching species and oxygen.

Claim 21

The process of claim 15, wherein the step of providing a silicide blocking layer comprises depositing a layer of silicon nitride.