Sub-micron bonded SOI by trench planarization

Claim 1

A process comprising the steps of: providing a substrate with a handle wafer having an upper surface and a lower surface and a device wafer having an upper surface and a lower surface, said lower surface of said device water disposed opposite the upper surface of said handle wafer and an oxide layer disposed between the handle wafer and the device wafer and bonded to the opposing surfaces of each water; forming a plurality of device regions on the upper surface of the device wafer, said device regions spaced from each other and each having a lower surface in contact with the oxide layer, an upper surface spaced from the oxide layer and raised sidewalls extending from the lower surface to the upper surface with portions of the oxide layer exposed in the spacings between the device regions and said upper surfaces being a level for at least two device regions; covering the device regions and the exposed oxide layer with a conformal, continuous, unbroken polish stop layer of a predetermined thickness wherein the level of the polish stop layer on the exposed oxide layer corresponds to the thickness of the polish stop layer; prior to patterning or removing any of the stop layer, planarizing the device regions by a step consisting essentially of polishing said continuous, unbroken stop layer and said device regions to the thickness of the polish stop layer on the oxide layer wherein said planarizing step consists essentially of polishing at a first pressure to remove the polish stop layer over the device areas and to remove the polish stop layer on the side walls of the device areas followed by a polishing at a second pressure, less than said first pressure, for reducing the levels of the device areas to the level of the polish stop layer between the device areas.

Claim 11

A method for forming a silicon on insulator substrate comprising: providing a handle silicon substrate; providing a silicon substrate suitable forming microelectronic devices; bonding the device substrate to the handle substrate by providing an oxide layer that bonds a surface of one substrate to the surface of the other substrate; reducing the thickness of the device substrate to form a layer of device silicon of a predetermined range of thickness; masking the device layer with a first resist layer to define field and device areas; removing unmasked portions of the device silicon layer to form the field areas, to form device areas with different levels and with raised sidewalls, and to expose the oxide layer between the two substrates; providing a conformal, continuous, unbroken polish stop layer of a predetermined thickness on the device and oxide layers wherein the level of the polish stop layer on the exposed oxide layer corresponds to the thickness of the polish stop layer; removing portions of the continuous, unbroken polish stop layer and the device silicon to planarize the device silicon down to the polish stop layer on the oxide layer wherein said removing step includes polishing at a first pressure to remove the polish stop layer over the device areas and to remove the polish stop layer on the side walls of the device areas followed by a polishing at a second pressure, less than said first pressure, for reducing the levels of the device areas to the level of the polish stop layer between the device areas.

Claim 12

A method for forming a silicon on insulator substrate comprising: providing a handle silicon substrate; providing a silicon substrate suitable forming microelectronic devices; bonding the device substrate to the handle substrate by providing an oxide layer that bonds a surface of one substrate to the surface of the other substrate; reducing the thickness of the device substrate to form a layer of device silicon of a predetermined range of thickness; masking the device layer with a first resist layer to define field and device areas; removing unmasked portions of the device silicon layer to form the field areas, to form device areas with different levels and with raised sidewalls, and to expose the oxide layer between the two substrates; providing a conformal, continuous, unbroken polish stop layer of a predetermined thickness on the device and oxide layers wherein the level of the polish stop layer on the exposed oxide layer corresponds to the thickness of the polish stop layer; removing portions of the continuous, unbroken polish stop layer and the device silicon to planarize the device silicon down to the polish stop layer on the oxide layer wherein said removing step includes polishing at a first pressure to remove the polish stop layer over the device areas and to remove the polish stop layer on the side walls of the device areas followed by a polishing at a second pressure, less than said first pressure, for reducing the levels of the device areas to the level of the polish stop layer between the device areas.