Method of manufacturing a SOI DRAM

Claim 1

A method of manufacturing a semiconductor memory device, comprising the sequential steps of: sequentially depositing a first insulating layer and a first conducting layer on a semiconductor substrate and forming a bit line by etching an exposed portion of said first conducting layer using a patterning process; depositing a second insulating layer on the first insulating layer and the bit line and forming a contact hole for connecting said bit line by etching an exposed portion of said second insulating layer using a patterning process; depositing polysilicon on the second insulating layer and the bit line contact hole and forming an active region by etching an exposed portion of said polysilicon using a patterning process; forming a gate insulating layer on said active region; sequentially depositing a second conducting layer and a third insulating layer on said gate insulating layer and forming a gate electrode by etching an exposed portion of said second conducting layer and said third insulating layer using a patterning process; forming a source region and a drain region by implanting an impurity in said active region; forming a spacer insulating layer on a sidewall of said gate electrode by depositing a fourth insulating layer on the resulting structure and then anisotropically etching said fourth insulating layer, and depositing a fifth insulating layer on the resulting structure; forming a charge storage contact by etching an exposed portion of said fifth insulating layer and said gate insulating layer using a contact mask; and forming a charge storage electrode by depositing a third conducting layer on the resulting structure and etching an exposed portion of said third conducting layer using a patterning process, and then sequentially forming a capacitor insulating layer and a plate electrode on said charge storage electrode.

Claim 2

A method of manufacturing a semiconductor memory device, comprising the sequential steps of: sequentially depositing a first insulating layer and a first conducting layer on a semiconductor substrate and forming a bit line by etching an exposed portion of said first conducting layer using a patterning process; depositing a second insulating layer on the first insulating layer and the bit line and forming a contact hole for connecting said bit line by etching an exposed portion of said second insulating layer using a patterning process; depositing polysilicon on the second insulating layer and the bit line contact hole and forming an active region by etching an exposed portion of said polysilicon using a patterning process; forming a gate insulating layer on said active region; sequentially depositing a second conducting layer and a third insulating layer on said gate insulating layer and forming a gate electrode by etching an exposed portion of said second conducting layer and said third insulating layer using a patterning process; forming a source region and a drain region by implanting an impurity in said active region; forming a spacer insulating layer on a sidewall of said gate electrode by depositing a fourth insulating layer on the resulting structure and then anisotropically etching said fourth insulating layer, and depositing a fifth insulating layer on the resulting structure; forming a charge storage contact by etching an exposed portion of said fifth insulating layer and said gate insulating layer using a contact mask; and forming a charge storage electrode by depositing a third conducting layer on the resulting structure and etching an exposed portion of said third conducting layer using a patterning process, and then sequentially forming a capacitor insulating layer and a plate electrode on said charge storage electrode.

Claim 5

A method of manufacturing a semiconductor memory device, comprising the sequential steps of: forming a bit line on a portion of a semiconductor substrate by an ion implanting method, with said bit line having the type opposite to that of said semiconductor substrate; depositing a first insulating layer on said semiconductor substrate and forming a contact hole for connecting said bit line by etching an exposed portion of said first insulating layer using a mask and etching process; depositing polysilicon on the first insulating layer and the bit line contact hole and forming an active region by etching an exposed portion of said polysilicon using a mask and etching process and then forming a gate insulating layer on said active region; sequentially forming a first conducting layer and a second insulating layer on said gate insulating layer and forming a gate electrode by etching an exposed portion of said second insulating layer and said first conducting layer using a patterning process; forming a source region and a drain region by implanting an impurity into said active region; forming a spacer insulating layer on the sidewall of said gate electrode by depositing a third insulating layer on the resulting structure and anisotropically etching said third insulating layer, and depositing a fourth insulating layer on the resulting structure; forming a charge storage contact by etching an exposed portion of said fourth insulating layer and gate insulating layer using a contact mask; and forming a charge storage electrode by depositing a second conducting layer on the resulting structure and etching an exposed portion of said second conducting layer by means of a patterning process, and sequentially forming a capacitor insulating layer and a plate electrode on said charge storage electrode.

Claim 6

A method of manufacturing a semiconductor memory device, comprising the sequential steps of: forming a bit line on a portion of a semiconductor substrate by an ion implanting method, with said bit line having the type opposite to that of said semiconductor substrate; depositing a first insulating layer on said semiconductor substrate and forming a contact hole for connecting said bit line by etching an exposed portion of said first insulating layer using a mask and etching process; depositing polysilicon on the first insulating layer and the bit line contact hole and forming an active region by etching an exposed portion of said polysilicon using a mask and etching process and then forming a gate insulating layer on said active region; sequentially forming a first conducting layer and a second insulating layer on said gate insulating layer and forming a gate electrode by etching an exposed portion of said second insulating layer and said first conducting layer using a patterning process; forming a source region and a drain region by implanting an impurity into said active region; forming a spacer insulating layer on the sidewall of said gate electrode by depositing a third insulating layer on the resulting structure and anisotropically etching said third insulating layer, and depositing a fourth insulating layer on the resulting structure; forming a charge storage contact by etching an exposed portion of said fourth insulating layer and gate insulating layer using a contact mask; and forming a charge storage electrode by depositing a second conducting layer on the resulting structure and etching an exposed portion of said second conducting layer by means of a patterning process, and sequentially forming a capacitor insulating layer and a plate electrode on said charge storage electrode.

Claim 9

A method of manufacturing a semiconductor memory device, comprising the sequential steps of: sequentially depositing a first insulating layer and a first conducting layer on a semiconductor substrate and forming a bit line by etching an exposed portion of said first conducting layer using a patterning process; depositing a second insulating layer on the first insulating layer and the bit line and forming a contact hole for connecting said bit line by etching an exposed portion of said second insulating layer using a patterning process; depositing polysilicon on the second insulating layer and the bit line contact hole and forming an active region by etching an exposed portion of said polysilicon using a patterning process; annealing said active region to singly crystallize said polysilicon; forming a gate insulating layer on said active region; sequentially depositing a second conducting layer and a third insulating layer on said gate insulating layer and forming a gate electrode by etching an exposed portion of said second conducting layer and said third insulating layer using a patterning process; forming a source region and a drain region by implanting an impurity into said active region; forming a spacer insulating layer on the side wall of said gate electrode by depositing a fourth insulating layer on the resulting structure and then anisotropically etching said fourth insulating layer, and depositing a fifth insulating layer on the resulting structure; forming a charge storage contact by etching an exposed portion of said fifth insulating layer and said gate insulating layer using a contact mask; and forming a charge storage electrode by depositing a third conducting layer on the resulting structure and etching an exposed portion of said third conducting layer using a patterning process, and then sequentially forming a capacitor insulating layer and a plate electrode on said charge storage electrode.

Claim 10

A method of manufacturing a semiconductor memory device, comprising the sequential steps of: sequentially depositing a first insulating layer and a first conducting layer on a semiconductor substrate and forming a bit line by etching an exposed portion of said first conducting layer using a patterning process; depositing a second insulating layer on the first insulating layer and the bit line and forming a contact hole for connecting said bit line by etching an exposed portion of said second insulating layer using a patterning process; depositing polysilicon on the second insulating layer and the bit line contact hole and forming an active region by etching an exposed portion of said polysilicon using a patterning process; annealing said active region to singly crystallize said polysilicon; forming a gate insulating layer on said active region; sequentially depositing a second conducting layer and a third insulating layer on said gate insulating layer and forming a gate electrode by etching an exposed portion of said second conducting layer and said third insulating layer using a patterning process; forming a source region and a drain region by implanting an impurity into said active region; forming a spacer insulating layer on the side wall of said gate electrode by depositing a fourth insulating layer on the resulting structure and then anisotropically etching said fourth insulating layer, and depositing a fifth insulating layer on the resulting structure; forming a charge storage contact by etching an exposed portion of said fifth insulating layer and said gate insulating layer using a contact mask; and forming a charge storage electrode by depositing a third conducting layer on the resulting structure and etching an exposed portion of said third conducting layer using a patterning process, and then sequentially forming a capacitor insulating layer and a plate electrode on said charge storage electrode.

Claim 14

A method of manufacturing a semiconductor memory device, comprising the sequential steps of: sequentially depositing a first insulating layer and a first conducting layer on a semiconductor substrate and forming a bit line by etching an exposed portion of said first conducting layer using a patterning process; depositing a second insulating layer on the first insulating layer and the bit line and forming a contact hole for connecting said bit line by etching an exposed portion of said second insulating layer using a patterning process; depositing polysilicon on the second insulating layer and the bit line contact hole and forming an active region by etching an exposed portion of said polysilicon using a patterning process; forming a gate insulating layer on said active region; depositing a second conducting layer on said gate insulating layer and forming a gate electrode by etching an exposed portion of said second conducting layer using a patterning process; forming a source region and a drain region by implanting an impurity into said active region; depositing a third insulating layer on the resulting structure; forming a charge storage contact by etching an exposed portion of said third insulating layer and said gate insulating layer using a contact mask; and forming a charge storage electrode by depositing a third conducting layer on the resulting structure and etching an exposed portion of said third conducting layer using a patterning process, and then sequentially forming a capacitor insulating layer and a plate electrode on said charge storage electrode.

Claim 15

A method of manufacturing a semiconductor memory device, comprising the sequential steps of: sequentially depositing a first insulating layer and a first conducting layer on a semiconductor substrate and forming a bit line by etching an exposed portion of said first conducting layer using a patterning process; depositing a second insulating layer on the first insulating layer and the bit line and forming a contact hole for connecting said bit line by etching an exposed portion of said second insulating layer using a patterning process; depositing polysilicon on the second insulating layer and the bit line contact hole and forming an active region by etching an exposed portion of said polysilicon using a patterning process; forming a gate insulating layer on said active region; depositing a second conducting layer on said gate insulating layer and forming a gate electrode by etching an exposed portion of said second conducting layer using a patterning process; forming a source region and a drain region by implanting an impurity into said active region; depositing a third insulating layer on the resulting structure; forming a charge storage contact by etching an exposed portion of said third insulating layer and said gate insulating layer using a contact mask; and forming a charge storage electrode by depositing a third conducting layer on the resulting structure and etching an exposed portion of said third conducting layer using a patterning process, and then sequentially forming a capacitor insulating layer and a plate electrode on said charge storage electrode.

Claim 19

A method of manufacturing a semiconductor memory device, comprising the sequential steps of: sequentially depositing a first insulating layer and a first conducting layer on a semiconductor substrate and forming a bit line by etching an exposed portion of said first conducting layer using a patterning process; depositing a second insulating layer on the first insulating layer and the bit line and forming a contact hole for connecting said bit line by etching an exposed portion of said second insulating layer using a patterning process; depositing polysilicon on the second insulating layer and the bit line contact hole and forming an active region by etching an exposed portion of said polysilicon using a patterning process; annealing said active region to singly crystallize said polysilicon; forming a gate insulating layer on said active region; depositing a second conducting layer on said gate insulating layer and forming a gate electrode by etching an exposed portion of said second conducting layer using a patterning process; forming a source region and a drain region by implanting an impurity into said active region; depositing a third insulating layer on the resulting structure; forming a charge storage contact by etching an exposed portion of said third insulating layer and said gate insulating layer using a contact mask; and forming a charge storage electrode by depositing a third conducting layer on the resulting structure and etching an exposed portion of said third conducting layer using a patterning process, and then sequentially forming a capacitor insulating layer and a plate electrode on said charge storage electrode.

Claim 20

A method of manufacturing a semiconductor memory device, comprising the sequential steps of: sequentially depositing a first insulating layer and a first conducting layer on a semiconductor substrate and forming a bit line by etching an exposed portion of said first conducting layer using a patterning process; depositing a second insulating layer on the first insulating layer and the bit line and forming a contact hole for connecting said bit line by etching an exposed portion of said second insulating layer using a patterning process; depositing polysilicon on the second insulating layer and the bit line contact hole and forming an active region by etching an exposed portion of said polysilicon using a patterning process; annealing said active region to singly crystallize said polysilicon; forming a gate insulating layer on said active region; depositing a second conducting layer on said gate insulating layer and forming a gate electrode by etching an exposed portion of said second conducting layer using a patterning process; forming a source region and a drain region by implanting an impurity into said active region; depositing a third insulating layer on the resulting structure; forming a charge storage contact by etching an exposed portion of said third insulating layer and said gate insulating layer using a contact mask; and forming a charge storage electrode by depositing a third conducting layer on the resulting structure and etching an exposed portion of said third conducting layer using a patterning process, and then sequentially forming a capacitor insulating layer and a plate electrode on said charge storage electrode.

Claim 24

A method of manufacturing a semiconductor memory device, comprising the sequential steps of; forming a bit line on a portion of a doped semiconductor substrate by an ion implantation method, with said bit line having a conductivity type opposite to that of said semiconductor substrate; depositing a first insulating layer on said semiconductor substrate and forming a contact hole for connecting said bit line by etching an exposed portion of said first insulating layer using a mask and etching process; depositing polysilicon on the first insulating layer and the bit line contact hole and forming an active region by etching an exposed portion of said polysilicon using a mask and etching process and then forming a gate insulating layer on said active region; forming a first conducting layer on said gate insulating layer and forming a gate electrode by etching an exposed portion of said first conducting layer using a patterning process; forming a source region and a drain region by implanting an impurity into said active region; depositing a second insulating layer on the resulting structure; forming a charge storage contact by etching an exposed portion of said second insulating layer and said gate insulating layer using a contact mask; and forming a charge storage electrode by depositing a second conducting layer on the resulting structure and etching an exposed portion of said second conducting layer by means of a patterning process and sequentially forming a capacitor insulating layer and a plate electrode on said charge storage electrode.

Claim 25

A method of manufacturing a semiconductor memory device, comprising the sequential steps of; forming a bit line on a portion of a doped semiconductor substrate by an ion implantation method, with said bit line having a conductivity type opposite to that of said semiconductor substrate; depositing a first insulating layer on said semiconductor substrate and forming a contact hole for connecting said bit line by etching an exposed portion of said first insulating layer using a mask and etching process; depositing polysilicon on the first insulating layer and the bit line contact hole and forming an active region by etching an exposed portion of said polysilicon using a mask and etching process and then forming a gate insulating layer on said active region; forming a first conducting layer on said gate insulating layer and forming a gate electrode by etching an exposed portion of said first conducting layer using a patterning process; forming a source region and a drain region by implanting an impurity into said active region; depositing a second insulating layer on the resulting structure; forming a charge storage contact by etching an exposed portion of said second insulating layer and said gate insulating layer using a contact mask; and forming a charge storage electrode by depositing a second conducting layer on the resulting structure and etching an exposed portion of said second conducting layer by means of a patterning process and sequentially forming a capacitor insulating layer and a plate electrode on said charge storage electrode.

Claim 28

A method of manufacturing a semiconductor memory device, comprising the sequential steps of: forming a bit line on a portion of a doped semiconductor substrate by an ion implantation method, with said bit line having a conductivity type opposite to that of said semiconductor substrate; depositing a first insulating layer on said semiconductor substrate and forming a contact hole for connecting said bit line by etching an exposed portion of said first insulating layer using a mask and etching process; depositing polysilicon on the first insulating layer and the bit line contact hole and forming an active region by etching an exposed portion of said polysilicon using a mask and etching process; annealing said active region to singly crystallize said polysilicon; forming a gate insulating layer on said active region; forming a first conducting layer on said gate insulating layer and forming a gate electrode by etching an exposed portion of said first conducting layer using a patterning process; forming a source region and a drain region by implanting an impurity into said active region; depositing a second insulating layer on the resulting structure; forming a charge storage contact by etching an exposed portion of said second insulating layer and said gate insulating layer using a contact mask; and forming a charge storage electrode by depositing a second conducting layer on the resulting structure and etching an exposed portion of said second conducting layer by means of a patterning process, and sequentially forming a capacitor insulating layer and a plate electrode on said charge storage electrode.

Claim 29

A method of manufacturing a semiconductor memory device, comprising the sequential steps of: forming a bit line on a portion of a doped semiconductor substrate by an ion implantation method, with said bit line having a conductivity type opposite to that of said semiconductor substrate; depositing a first insulating layer on said semiconductor substrate and forming a contact hole for connecting said bit line by etching an exposed portion of said first insulating layer using a mask and etching process; depositing polysilicon on the first insulating layer and the bit line contact hole and forming an active region by etching an exposed portion of said polysilicon using a mask and etching process; annealing said active region to singly crystallize said polysilicon; forming a gate insulating layer on said active region; forming a first conducting layer on said gate insulating layer and forming a gate electrode by etching an exposed portion of said first conducting layer using a patterning process; forming a source region and a drain region by implanting an impurity into said active region; depositing a second insulating layer on the resulting structure; forming a charge storage contact by etching an exposed portion of said second insulating layer and said gate insulating layer using a contact mask; and forming a charge storage electrode by depositing a second conducting layer on the resulting structure and etching an exposed portion of said second conducting layer by means of a patterning process, and sequentially forming a capacitor insulating layer and a plate electrode on said charge storage electrode.

Claim 32

A method of manufacturing a semiconductor memory device, comprising the sequential steps of: forming a bit line on a portion of a doped semiconductor substrate by an ion implantation method, with said bit line having the a conductivity type opposite to that of said semiconductor substrate; depositing a first insulating layer on said semiconductor substrate and forming a contact hole for connecting said bit line by etching an exposed portion of said first insulating layer using a mask and etching process; depositing polysilicon on the first insulating layer and the bit line contact hole and forming an active region by etching an exposed portion of said polysilicon using a mask and etching process and then forming a gate insulating layer on said active region; annealing said active region to singly crystalize said polysilicon; sequentially forming a first conducting layer and a second insulating layer on said gate insulating layer and forming a gate electrode by etching an exposed portion of said second insulating layer and said first conducting layer using a patterning process; forming a source region and a drain region by implanting an impurity into said active region; forming a spacer insulating layer on the sidewall of said gate electrode by depositing a third insulating layer on the resulting structure and anisotropically etching said third insulating layer, and depositing a fourth insulating layer on the resulting structure; forming a charge storage contact by etching an exposed portion of said fourth insulating layer and gate insulating layer using a contact mask; and forming a charge storage electrode by depositing a second conducting layer on the resulting structure and etching an exposed portion of said second conducting layer by means of a patterning process, and sequentially forming a capacitor insulating layer and a plate electrode on said charge storage electrode.

Claim 33

A method of manufacturing a semiconductor memory device, comprising the sequential steps of: forming a bit line on a portion of a doped semiconductor substrate by an ion implantation method, with said bit line having the a conductivity type opposite to that of said semiconductor substrate; depositing a first insulating layer on said semiconductor substrate and forming a contact hole for connecting said bit line by etching an exposed portion of said first insulating layer using a mask and etching process; depositing polysilicon on the first insulating layer and the bit line contact hole and forming an active region by etching an exposed portion of said polysilicon using a mask and etching process and then forming a gate insulating layer on said active region; annealing said active region to singly crystalize said polysilicon; sequentially forming a first conducting layer and a second insulating layer on said gate insulating layer and forming a gate electrode by etching an exposed portion of said second insulating layer and said first conducting layer using a patterning process; forming a source region and a drain region by implanting an impurity into said active region; forming a spacer insulating layer on the sidewall of said gate electrode by depositing a third insulating layer on the resulting structure and anisotropically etching said third insulating layer, and depositing a fourth insulating layer on the resulting structure; forming a charge storage contact by etching an exposed portion of said fourth insulating layer and gate insulating layer using a contact mask; and forming a charge storage electrode by depositing a second conducting layer on the resulting structure and etching an exposed portion of said second conducting layer by means of a patterning process, and sequentially forming a capacitor insulating layer and a plate electrode on said charge storage electrode.