US5583786A
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US
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Apparatus and method for testing integrated circuits
Assignee: Intel Corp
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Filing: 1993-12-30
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Granted: 1996-12-10
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Expires: 2013-12-30
Abstract
Abstract A testing methodology for very large scale integrated circuits, for example, microprocessors having several million transistors. Initially a set of pseudorandom test patterns is selected. During the design of the integrated circuit it is partitioned into functional units and each unit is designed to be verified and tested by the test patterns. During a test mode all of the units of the integrated circuit receives the test patterns in parallel. The output from each unit is coupled to a signature register. The contents of the signature registers are examined following application of the test pattern. This testing methodology lends itself to the simultaneous testing of many integrated circuits.
Inventors
- 👤 Wayne Needham
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 15:34
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/22; G06F11/2205; G06F11/2236; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/3183; G06F2201/00; G06F2201/83
Claims Analysis
Total Claims: 19
Claim 1
Independent Claim
102 words
A method for designing an integrated circuit comprising the steps of: partitioning a portion of the circuit into functional units; selecting a set of pseudorandom test patterns; designing the units such that each unit can be tested by the pseudorandom patterns; providing each of the units with a memory; providing a test mode on the integrated circuit for simultaneously coupling the test patterns to the units and for causing the units to generate outputs in response to the test patterns; coupling the outputs of each unit to the memory of each unit; and providing a mechanism for reading data from the memory.
Claim 2
Independent Claim
102 words
A method for designing an integrated circuit comprising the steps of: partitioning a portion of the circuit into functional units; selecting a set of pseudorandom test patterns; designing the units such that each unit can be tested by the pseudorandom patterns; providing each of the units with a memory; providing a test mode on the integrated circuit for simultaneously coupling the test patterns to the units and for causing the units to generate outputs in response to the test patterns; coupling the outputs of each unit to the memory of each unit; and providing a mechanism for reading data from the memory.
Claim 3
Dependent Claim
30 words
The method of claim 1 wherein the step of designing the units includes verifying the design of the units with the test patterns prior to fabrication of the integrated circuit.
Claim 4
Dependent Claim
83 words
An integrated circuit comprising: a plurality of functional units, each unit including a signature register for recording the response of the unit to input signals; a bus for receiving a predetermined set of test patterns and for coupling in parallel the test patterns to each unit; each unit being adapted to respond to the same set of predetermined test patterns when the set is applied as input signals to the unit; and a test mechanism for reading the contents of the signature registers.
Claim 5
Dependent Claim
83 words
An integrated circuit comprising: a plurality of functional units, each unit including a signature register for recording the response of the unit to input signals; a bus for receiving a predetermined set of test patterns and for coupling in parallel the test patterns to each unit; each unit being adapted to respond to the same set of predetermined test patterns when the set is applied as input signals to the unit; and a test mechanism for reading the contents of the signature registers.
Claim 6
Dependent Claim
40 words
The integrated circuit defined by claim 3 wherein the bus is adapted for receiving the test patterns and for coupling in parallel the test patterns to the units upon the application of a test mode signal to the integrated circuit.
Claim 7
Dependent Claim
33 words
The integrated circuit defined by claim 4 wherein the signature registers are coupled in series to a terminal on the integrated circuit for reading the contents of the signature registers at the terminal.
Claim 8
Dependent Claim
16 words
The integrated circuit defined by claim 5 wherein each of the signature registers includes linear feedback.
Claim 9
Dependent Claim
12 words
The integrated circuit of claim 6 wherein the test patterns are pseudorandom.
Claim 10
Independent Claim
93 words
A method for providing testability for an integrated circuit comprising the steps of: selecting a set of pseudorandom test patterns each pattern comprising a plurality of bits; partitioning part of the integrated circuit into a plurality of functional units; assuring that each of the functional units is testable by the test patterns; applying the test patterns to the integrated circuit such that each unit receives some of the bits of each pattern; storing signals representing the response of each of the units to the bits; and, examining the stored signals representing the responses.
Claim 11
Independent Claim
93 words
A method for providing testability for an integrated circuit comprising the steps of: selecting a set of pseudorandom test patterns each pattern comprising a plurality of bits; partitioning part of the integrated circuit into a plurality of functional units; assuring that each of the functional units is testable by the test patterns; applying the test patterns to the integrated circuit such that each unit receives some of the bits of each pattern; storing signals representing the response of each of the units to the bits; and, examining the stored signals representing the responses.
Claim 12
Dependent Claim
24 words
The method defined by claim 8 wherein the step of applying the test patterns includes the generation of the test patterns by an algorithm.
Claim 13
Dependent Claim
17 words
The method defined by claim 9 wherein the step of storing signals includes storing in signature registers.
Claim 14
Dependent Claim
112 words
In an integrated circuit that includes a plurality of multiple input signature registers for storing responses to input test patterns, an improved method for testing the integrated circuit comprising the steps of: partitioning a portion of the integrated circuit into functional units, each functional unit being coupled to a signature register for providing its outputs thereto; assuring that each of the units is testable by a set of test patterns; simultaneously applying the set of test patterns to the units and in response storing the outputs of each unit to its respective signature register; and, examining the contents of the signature registers after the test patterns have been applied to the units.
Claim 15
Dependent Claim
112 words
In an integrated circuit that includes a plurality of multiple input signature registers for storing responses to input test patterns, an improved method for testing the integrated circuit comprising the steps of: partitioning a portion of the integrated circuit into functional units, each functional unit being coupled to a signature register for providing its outputs thereto; assuring that each of the units is testable by a set of test patterns; simultaneously applying the set of test patterns to the units and in response storing the outputs of each unit to its respective signature register; and, examining the contents of the signature registers after the test patterns have been applied to the units.
Claim 16
Dependent Claim
14 words
The method defined by claim 11 wherein the set of test patterns are pseudorandom.
Claim 17
Dependent Claim
15 words
The method defined by claim 12 wherein the pseudorandom patterns are generated by an algorithm.
Claim 18
Dependent Claim
116 words
In an integrated circuit having a plurality of functional units, an improvement of the integrated circuit for testing the circuit comprising: a bus for directing input test patterns applied to the circuit to each of the units when a test mode is selected; each of the units being coupled to receive the input test patterns from the bus and to process the test patterns to provide output signals; a storage means for each of the units, for receiving the output signals from its respective unit, the storage means providing a test signature for its respective unit; and, read out means coupled to the storage means for reading out the test signatures from each of the units.
Claim 19
Dependent Claim
116 words
In an integrated circuit having a plurality of functional units, an improvement of the integrated circuit for testing the circuit comprising: a bus for directing input test patterns applied to the circuit to each of the units when a test mode is selected; each of the units being coupled to receive the input test patterns from the bus and to process the test patterns to provide output signals; a storage means for each of the units, for receiving the output signals from its respective unit, the storage means providing a test signature for its respective unit; and, read out means coupled to the storage means for reading out the test signatures from each of the units.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-12-10 | 2000-06-10 | 2000-12-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-12-10 | 2004-06-10 | 2004-12-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-12-10 | 2008-06-10 | 2008-12-10 | $7700.00 | Window Closed / Lapsed |