US5581773A
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US
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Massively parallel SIMD processor which selectively transfers individual contiguously disposed serial memory elements
Assignee: Individual
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Filing: 1992-05-12
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Granted: 1996-12-03
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Expires: 2012-05-12
Abstract
Abstract A parallel processor adapted to be used as a vector co-processor to a host computer, comprising a plurality of 1-bit processing elements (PEs) and an associated rapidly accessed memory and lateral data path switch providing rapid computational processing of data contained within contiguous bit locations of each 1-bit, and rapid lateral transfer between 1-bit PEs. The PEs implement the data logical and computational processing with a reduced instruction set. Rapid data transfer between the PE and the associated memory is provided by implementing such elements on a common semi-conductor substrate having shared data address and control signals, thus reducing the complexity of circuitry external to the chip. Flexible and rapid data transfer between and among PEs is provided with a switch element comprising a cross-bar which allows the parallel processor to provide rapid processing of video and other data. A preferred embodiment discussed herein implements the parallel processor using multi-port video DRAM devices as column-aligned parallel processors.
Inventors
- 👤 Michael A. Glover
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 09:34
CPC Classifications
G; G06; G06F; G06F15/00; G06F15/76; G06F15/80; G06F15/8007; G06F15/8015
Claims Analysis
Total Claims: 33
Claim 1
Independent Claim
58 words
A SIMD processor comprising: a plurality of single-bit memories each having contiguously disposed serial memory elements; and a plurality of single-bit non-arithmetic, conditional data transfer processing elements, each connected to receive contiguous serial data elements from a corresponding one of said single-bit memories; and a cross-bar switch connected to selectively transfer serial data between said single-bit processing elements.
Claim 2
Dependent Claim
58 words
A SIMD processor comprising: a plurality of single-bit memories each having contiguously disposed serial memory elements; and a plurality of single-bit non-arithmetic, conditional data transfer processing elements, each connected to receive contiguous serial data elements from a corresponding one of said single-bit memories; and a cross-bar switch connected to selectively transfer serial data between said single-bit processing elements.
Claim 3
Dependent Claim
22 words
The SIMD processor of claim 1, wherein said processing elements comprise a plurality of data registers including a conditionally storable data register.
Claim 4
Dependent Claim
20 words
The SIMD processor of claim 2, wherein said conditionally storable data register is responsive to data register resident mask data.
Claim 5
Dependent Claim
14 words
The SIMD processor of claim 3, comprising two data registers and one mask register.
Claim 6
Dependent Claim
24 words
The SIMD processor of claim 1, wherein, said plurality of single-bit memories and single-bit processing elements are arranged to form a single integrated circuit.
Claim 7
Dependent Claim
19 words
The SIMD processor of claim 1, wherein said contiguously disposed serial memory elements are accessible by a common address.
Claim 8
Dependent Claim
151 words
A SIMD processor comprising: a plurality of addressable 1-bit×N location memory elements; a plurality of 1-bit processing elements each connected to receive a selected serial contiguous data elements from a corresponding said 1-bit memory, wherein each said 1-bit processing elements includes a mask bit register and a data register conditionally loadable in response to the contents of said mask-bit register, providing the operations comprising copy, or, invert, including selected bits in said 1-bit memory; and a processing element controller having a corresponding instruction set and being connected to said plurality of 1-bit processing elements mask and data registers and said plurality of 1-bit×N memory elements for providing a selected sequence of non-arithmetic, conditional processing element data transfers, which plurality conditional processing element data transfers together provides a corresponding one of a plurality of logical and arithmetic operations comprising data copy, conditional data copy, and, or, invert, add, subtract, multiply and divide.
Claim 9
Dependent Claim
151 words
A SIMD processor comprising: a plurality of addressable 1-bit×N location memory elements; a plurality of 1-bit processing elements each connected to receive a selected serial contiguous data elements from a corresponding said 1-bit memory, wherein each said 1-bit processing elements includes a mask bit register and a data register conditionally loadable in response to the contents of said mask-bit register, providing the operations comprising copy, or, invert, including selected bits in said 1-bit memory; and a processing element controller having a corresponding instruction set and being connected to said plurality of 1-bit processing elements mask and data registers and said plurality of 1-bit×N memory elements for providing a selected sequence of non-arithmetic, conditional processing element data transfers, which plurality conditional processing element data transfers together provides a corresponding one of a plurality of logical and arithmetic operations comprising data copy, conditional data copy, and, or, invert, add, subtract, multiply and divide.
Claim 10
Dependent Claim
28 words
The SIMD processor of claim 7, wherein said memory locations and said processing elements operative according to said programmed instruction set provides add, subtract, multiply, divide, square root.
Claim 11
Dependent Claim
21 words
The SIMD processor of claim 7, further including a cross-bar switch connected to selectively transfer data between said 1-bit processing elements.
Claim 12
Dependent Claim
39 words
The SIMD processor of claim 9, wherein a first integrated circuit includes said plurality of said 1-bit by N location memory elements and said plurality of 1-bit processing elements, and wherein a second integrated circuit comprises said cross-bar switch.
Claim 13
Dependent Claim
27 words
The SIMD processor of claim 10, comprising 16 integrated circuits having said plurality of 1-bit by N location memory elements and said plurality of 1-bit processing elements.
Claim 14
Dependent Claim
51 words
A SIMD data format apparatus, comprising means for receiving sequential n-bit wide data words into a plurality of rows; means for rearranging the rows for uniform shift distance for all elements within a row; means for shifting data along the rows; and means for rearranging data along a plurality of columns.
Claim 15
Dependent Claim
51 words
A SIMD data format apparatus, comprising means for receiving sequential n-bit wide data words into a plurality of rows; means for rearranging the rows for uniform shift distance for all elements within a row; means for shifting data along the rows; and means for rearranging data along a plurality of columns.
Claim 16
Dependent Claim
24 words
The SIMD data format apparatus of claim 12, further including a plurality of processing elements for processing data stored in said means for receiving.
Claim 17
Dependent Claim
18 words
The SIMD data format apparatus of claim 13, wherein said plurality of processing elements receives said rearranged data.
Claim 18
Dependent Claim
24 words
The SIMD data format apparatus of claim 14, further including means for transferring processed data between said SIMD data format apparatus and external equipment.
Claim 19
Dependent Claim
15 words
The SIMD data format apparatus of claim 15, wherein said received data comprises image data.
Claim 20
Dependent Claim
136 words
A processor comprising: a memory element including a plurality of columns of contiguous addressable storage locations according to an address signal, an `M` register adapted to store a condition code, an `A` register adapted to conditionally receive data from one of said plurality of storage locations according to the contents of said `M` register, wherein said memory element includes means for logically inverting said data and performing at least one of a logical `and` and a logical `or`; and a control means connected to said memory element for providing arithmetic operations by a sequence of non-arithmetic, conditional logical memory and memory data transfers including a plurality of the operations by said `A` and `M` registers, wherein the arithmetic operations comprises data copy, conditional data copy, and, or, invert, add, subtract, multiply, divide and square root functions.
Claim 21
Dependent Claim
136 words
A processor comprising: a memory element including a plurality of columns of contiguous addressable storage locations according to an address signal, an `M` register adapted to store a condition code, an `A` register adapted to conditionally receive data from one of said plurality of storage locations according to the contents of said `M` register, wherein said memory element includes means for logically inverting said data and performing at least one of a logical `and` and a logical `or`; and a control means connected to said memory element for providing arithmetic operations by a sequence of non-arithmetic, conditional logical memory and memory data transfers including a plurality of the operations by said `A` and `M` registers, wherein the arithmetic operations comprises data copy, conditional data copy, and, or, invert, add, subtract, multiply, divide and square root functions.
Claim 22
Dependent Claim
23 words
The processor of claim 17, further including a `B` register for selectively receiving addressed data according to the contents of said `M` register.
Claim 23
Dependent Claim
19 words
The processor of claim 18, wherein said memory integrated circuit includes a plurality of `M`, `A` and `B` registers.
Claim 24
Dependent Claim
14 words
The processor of claim 17, wherein said memory element comprises a memory integrated circuit.
Claim 25
Dependent Claim
123 words
A processor comprising: a memory element including a plurality of columns of contiguous 1-bit storage locations addressable according to an address signal, a register adapted to conditionally receive data from one of said plurality of storage locations, wherein said memory element includes means for logically inverting said data and performing at least one of a logical `and` and a logical `or`; and a control means connected to said memory element for providing a selected sequence of non-arithmetic, conditional logical memory and memory data transfers, which together provides a corresponding one of a plurality of logical and arithmetic operations comprising data copy, conditional data copy, and, or, invert, add, subtract, multiply, divide, square root of data arranged along the column of contiguous storage locations.
Claim 26
Dependent Claim
123 words
A processor comprising: a memory element including a plurality of columns of contiguous 1-bit storage locations addressable according to an address signal, a register adapted to conditionally receive data from one of said plurality of storage locations, wherein said memory element includes means for logically inverting said data and performing at least one of a logical `and` and a logical `or`; and a control means connected to said memory element for providing a selected sequence of non-arithmetic, conditional logical memory and memory data transfers, which together provides a corresponding one of a plurality of logical and arithmetic operations comprising data copy, conditional data copy, and, or, invert, add, subtract, multiply, divide, square root of data arranged along the column of contiguous storage locations.
Claim 27
Dependent Claim
29 words
The processor of claim 21, further including a cross-bar switch for selectively transferring data between registers corresponding to different ones of said plurality of columns of 1-bit storage locations.
Claim 28
Dependent Claim
17 words
The processor of claim 22, further including program responsive means for reformatting row-contiguous data into column-contiguous data.
Claim 29
Dependent Claim
24 words
The processor of claim 22, wherein said register includes A, B and M registers in association with said column of contiguous 1-bit storage locations.
Claim 30
Independent Claim
43 words
A method of data processing, comprising the steps of: receiving sequential n-bit wide data words into rows and columns; rearranging the rows for uniform shift distance for all elements within a row; shifting data along the rows; and rearranging data along the columns.
Claim 31
Independent Claim
43 words
A method of data processing, comprising the steps of: receiving sequential n-bit wide data words into rows and columns; rearranging the rows for uniform shift distance for all elements within a row; shifting data along the rows; and rearranging data along the columns.
Claim 32
Dependent Claim
17 words
The method of claim 25, further including the step of arithmetically processing said data along said columns.
Claim 33
Dependent Claim
17 words
The method of claim 26, further including the step of logically processing said data along said columns.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-12-03 | 2000-06-03 | 2000-12-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-12-03 | 2004-06-03 | 2004-12-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-12-03 | 2008-06-03 | 2008-12-03 | $7700.00 | Window Closed / Lapsed |