Patent JPS64936A successfully refreshed from Google Patents.
US5299159A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Serial register stage arranged for connection with a single bitline
Assignee: Texas Instruments Inc
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Filing: 1992-06-29
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Granted: 1994-03-29
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Expires: 2012-06-29
Abstract
Abstract A dual-port memory includes an array of dynamic storage cells and a serial register having a plurality of static stages. Each stage of the serial register is arranged for receiving a data bit from a selected storage cell of the array. A plurality of bitlines is interposed between the storage cells of the array and the stages of the serial register. At one time only a single selectable bitline is arranged for interconnecting each of the columns of storage cells with each of the stages of the serial register. Each stage of the serial register includes a latch disabling circuit for selectively enabling and disabling coupling from an output of one amplifier to an input of another amplifier. By disabling such coupling, new data easily can be written into the serial register stage. A keeper circuit in each stage of the serial register reduces power consumption.
Inventors
- 👤 Anthony M. Balistreri
- 👤 Andre J. Guillemaud
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 17:38
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/10; G11C7/1075
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
92 words
A serial register stage comprising: a latch circuit having first and second MOS transistor amplifier circuits, each amplifier circuit including an input node and an output node; a lead connecting the output node of the first amplifier circuit with the input node of the second amplifier circuit; a latch disabling circuit for selectively enabling and disabling coupling between the output node of the second amplifier circuit and the input node of the first amplifier circuit; and a lead for applying an input signal to the input node of the first amplifier circuit.
Claim 2
Dependent Claim
92 words
A serial register stage comprising: a latch circuit having first and second MOS transistor amplifier circuits, each amplifier circuit including an input node and an output node; a lead connecting the output node of the first amplifier circuit with the input node of the second amplifier circuit; a latch disabling circuit for selectively enabling and disabling coupling between the output node of the second amplifier circuit and the input node of the first amplifier circuit; and a lead for applying an input signal to the input node of the first amplifier circuit.
Claim 3
Dependent Claim
46 words
A serial register stage, in accordance with claim 1, wherein the latch disabling circuit includes a latching gate, responsive to a control signal, for enabling or disabling coupling of the output node of the second amplifier circuit to the input node of the first amplifier circuit.
Claim 4
Dependent Claim
50 words
A serial register stage, in accordance with claim 2, further comprising: a circuit, connected between the output and input nodes of the first amplifier circuit, for assuring that potential levels on the input node of the first amplifier circuit are either a full supply potential level or at ground potential.
Claim 5
Dependent Claim
84 words
A serial register stage, in accordance with claim 3, further comprising: a bitline selection circuit having a plurality of inputs, each input connecting with a different single-sided bitline, and having a single output connecting with the input signal lead, and a plurality of control leads, each control lead arranged for applying a selection signal to the bitline selection circuit for enabling a data signal to be coupled from a selected one of the single-sided bitlines to the single output of the bitline selection circuit.
Claim 6
Dependent Claim
84 words
A serial register stage, in accordance with claim 2, further comprising: a bitline selection circuit having a plurality of inputs, each input connecting with a different single-sided bitline, and having a single output connecting with the input signal lead, and a plurality of control leads, each control lead arranged for applying a selection signal to the bitline selection circuit for enabling a data signal to be coupled from a selected one of the single-sided bitlines to the single output of the bitline selection circuit.
Claim 7
Dependent Claim
50 words
A serial register stage, in accordance with claim 1, further comprising: a circuit, connected between the output and input nodes of the first amplifier circuit, for assuring that potential levels on the input node of the first amplifier circuit are either a full supply potential level or at ground potential.
Claim 8
Dependent Claim
84 words
A serial register stage, in accordance with claim 1, further comprising: a bitline selection circuit having a plurality of inputs, each input connecting with a different single-sided bitline, and having a single output connecting with the input signal lead, and a plurality of control leads, each control lead arranged for applying a selection signal to the bitline selection circuit for enabling a data signal to be coupled from a selected one of the single-sided bitlines to the single output of the bitline selection circuit.
Claim 9
Dependent Claim
102 words
A serial register stage comprising: a latch circuit having first and second MOS transistor amplifier circuits, each amplifier circuit including an input node and an output node; a lead connecting the output node of the first amplifier circuit with the input node of the second amplifier circuit; a lead for applying an input signal to the input node of the first amplifier circuit; and a circuit, connected between the output and nodes of the first amplifier circuit, for assuring that potential levels on the input node of the first amplifier circuit are either a full supply potential level or at ground potential.
Claim 10
Dependent Claim
102 words
A serial register stage comprising: a latch circuit having first and second MOS transistor amplifier circuits, each amplifier circuit including an input node and an output node; a lead connecting the output node of the first amplifier circuit with the input node of the second amplifier circuit; a lead for applying an input signal to the input node of the first amplifier circuit; and a circuit, connected between the output and nodes of the first amplifier circuit, for assuring that potential levels on the input node of the first amplifier circuit are either a full supply potential level or at ground potential.
Claim 11
Dependent Claim
136 words
A serial register stage comprising: a latch circuit having first and second MOS transistor amplifier circuits, each amplifier circuit including an input node and an output node; a lead connecting the output node of the first amplifier circuit with the input node of the second amplifier circuit; a lead for applying an input signal to the input node of the first amplifier circuit; a bitline selection circuit having a plurality of inputs, each input connection with a different single-side bitline, and having a single output connecting with the input signal lead; and a plurality of control leads, each control lead arranged for applying a selection signal to the bitline selection circuit for enabling a data signal to be coupled from a selected one of the single-sided bitlines to the single output of the bitline selection circuit.
Claim 12
Dependent Claim
136 words
A serial register stage comprising: a latch circuit having first and second MOS transistor amplifier circuits, each amplifier circuit including an input node and an output node; a lead connecting the output node of the first amplifier circuit with the input node of the second amplifier circuit; a lead for applying an input signal to the input node of the first amplifier circuit; a bitline selection circuit having a plurality of inputs, each input connection with a different single-side bitline, and having a single output connecting with the input signal lead; and a plurality of control leads, each control lead arranged for applying a selection signal to the bitline selection circuit for enabling a data signal to be coupled from a selected one of the single-sided bitlines to the single output of the bitline selection circuit.
References Cited (Backward Citations)
US4984214A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-03-28 | 1997-09-27 | 1998-03-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-03-28 | 2001-09-27 | 2002-03-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-03-28 | 2005-09-27 | 2006-03-29 | $7700.00 | Window Closed / Lapsed |