US5581695A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Source-level run-time software code debugging instrument
Assignee: NXP USA Inc
•
Filing: 1994-07-07
•
Granted: 1996-12-03
•
Expires: 2014-07-07
Abstract
Abstract A source-level run-time software code debugging instrument (10) includes target access probe ("TAP") (12) and communications adapter ("COMDAP") (14) that process emulation commands provided by source-level debugging software operating on a host computer. The TAP includes a TAP CPU (28) that receives target CPU input signals and delivers target CPU output signals for controlling the execution of software code by the target circuit in accordance with command signals provided by the host computer. The TAP also includes programmable logic cell array (24) and RAM (34). The TAP logic cell array routes command and data signals to and from the TAP CPU, and the RAM stores an in-circuit emulation ("ICE") program used by the TAP to operate the target circuit. The COMDAP is physically separate from the TAP and provides an interface between the host computer and the TAP. The COMDAP includes a programmable logic cell array (44) and an EPROM (46). The COMDAP logic cell array routes command and data signals to and from the COMDAP, and the EPROM stores the commands for configuring the signal paths within the TAP and COMDAP logic cell arrays and stores the TAP ICE program. A flat cable assembly (16) provides a high-speed signal communications link between the TAP and the COMDAP. The TAP uses certain microprocessor signal features and source-level debugging software that runs on the host computer to provide a software engineer with a fully transparent window into the internal functioning of the TAP CPU while executing code in the target circuit environment.
Inventors
- 👤 Robin L. Knoke
- 👤 Marvin T. Johnson
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 01:06
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/36; G06F11/362; G06F11/3648; G06F11/3656
Claims Analysis
Total Claims: 113
Claim 1
Independent Claim
322 words
A target access probe ("TAP") for connecting to a target circuit that includes a target CPU communicating with a target program memory having memory sites that store main program instructions for exercising of target circuit components, the target CPU having input and output terminal positions at which respective specified target CPU input and output signals appear, the TAP testing and verifying the operational performance of software, in the target circuit in response to host command signals provided by a host computer in the electrical absence of the target CPU and comprising: a connector for electrically and mechanically connecting the TAP to the target circuit at the target CPU position, the connector being fixedly mounted on the TAP and being adapted for attachment directly to the target circuit so that the TAP is physically supported by the target circuit; a TAP CPU receiving target CPU input signals at the input terminal positions and delivering target CPU output signals at the output terminal positions; in-circuit emulation ("ICE") circuitry including ICE program memory sites that store ICE program instructions, the ICE circuity communicating with the TAP CPU for producing the target CPU output signals in accordance with the ICE program instructions executed by the TAP CPU in response to the host command signals; and an input and output signal link for providing a signal link to and from the host computer and for the target CPU input and output signals, the ICE program memory sites residing wholly outside of the target circuit and the target circuit address space, and the delivery of the target CPU input signals to the corresponding target CPU input terminal positions and the delivery of the target CPU output signals to the corresponding target CPU output positions in response to the host command signals providing a capability for testing and verifying the performance of the target circuit in accordance with the ICE program instructions independently of the target program stored therein.
Claim 2
Dependent Claim
322 words
A target access probe ("TAP") for connecting to a target circuit that includes a target CPU communicating with a target program memory having memory sites that store main program instructions for exercising of target circuit components, the target CPU having input and output terminal positions at which respective specified target CPU input and output signals appear, the TAP testing and verifying the operational performance of software, in the target circuit in response to host command signals provided by a host computer in the electrical absence of the target CPU and comprising: a connector for electrically and mechanically connecting the TAP to the target circuit at the target CPU position, the connector being fixedly mounted on the TAP and being adapted for attachment directly to the target circuit so that the TAP is physically supported by the target circuit; a TAP CPU receiving target CPU input signals at the input terminal positions and delivering target CPU output signals at the output terminal positions; in-circuit emulation ("ICE") circuitry including ICE program memory sites that store ICE program instructions, the ICE circuity communicating with the TAP CPU for producing the target CPU output signals in accordance with the ICE program instructions executed by the TAP CPU in response to the host command signals; and an input and output signal link for providing a signal link to and from the host computer and for the target CPU input and output signals, the ICE program memory sites residing wholly outside of the target circuit and the target circuit address space, and the delivery of the target CPU input signals to the corresponding target CPU input terminal positions and the delivery of the target CPU output signals to the corresponding target CPU output positions in response to the host command signals providing a capability for testing and verifying the performance of the target circuit in accordance with the ICE program instructions independently of the target program stored therein.
Claim 3
Dependent Claim
45 words
The TAP of claim 10 wherein the TAP further includes a rigid substrate, and wherein the connector, the TAP CPU, and the in-circuit emulation circuitry are physically mounted on the substrate so that the TAP is physically supported on the target circuit by the connector.
Claim 4
Dependent Claim
44 words
The TAP of claim 1 wherein the TAP CPU includes emulation specific circuitry specially adapted to perform emulation functions, and wherein the emulation specific circuitry of the TAP CPU is accessible externally of the TAP CPU and coupled to other circuitry on the TAP.
Claim 5
Dependent Claim
30 words
The TAP of claim 1 wherein the TAP CPU further performs the function of communicating directly with the host computer to receive the host command signals from the host computer.
Claim 6
Dependent Claim
20 words
The TAP of claim 1 wherein the ICE circuitry includes a memory containing at least one ICE program memory site.
Claim 7
Dependent Claim
36 words
The TAP of claim 1 wherein the ICE circuitry includes a random access memory containing the ICE program memory sites, and wherein the TAP CPU fetches the ICE program instructions directly from the random access memory.
Claim 8
Dependent Claim
22 words
The TAP of claim 1 wherein the TAP CPU is adapted to communicate with both the host computer and the target CPU.
Claim 9
Dependent Claim
25 words
The TAP of claim 1 wherein the ICE circuitry includes a memory into which the ICE program instructions are loaded upon initialization of the TAP.
Claim 10
Dependent Claim
19 words
The TAP of claim 8 wherein all of the ICE program instructions are loaded upon initialization of the TAP.
Claim 11
Dependent Claim
17 words
The TAP of claim 8 wherein multiple ICE program instructions are loaded upon initialization of the TAP.
Claim 12
Dependent Claim
19 words
The TAP of claim 8 wherein multiple instructions of the ICE program are loaded upon initialization of the TAP.
Claim 13
Dependent Claim
235 words
An instrument for testing and verifying the operational performance of software in a target computer system in the electrical absence of a target CPU having input and output terminal positions at which respective specified target CPU input and output signals appear, the instrument comprising: a target access probe ("TAP") including a TAP CPU receiving target CPU input signals and delivering target CPU output signals for controlling the execution of software code on the target computer system in accordance with command signals provided by a host analysis code source, the TAP including a connector for electrically connecting the TAP CPU to the target computer system at the target CPU position, the TAP further including a memory storing an in-circuit emulation ("ICE") program containing instructions for the TAP CPU in accordance with the command signals from the host analysis code source, the ICE program residing wholly within the memory and outside both the target computer system and the target computer address space during execution of the ICE program by the TAP CPU, the TAP further including a TAP signal routing integrated circuit for assembling the host command signals into a digital word format and routing the assembled command signals to the TAP CPU; a communications adapter that provides an interface between the host analysis code source and the TAP; and a data communication link for providing a data communication link between the TAP and the communications adapter.
Claim 14
Dependent Claim
235 words
An instrument for testing and verifying the operational performance of software in a target computer system in the electrical absence of a target CPU having input and output terminal positions at which respective specified target CPU input and output signals appear, the instrument comprising: a target access probe ("TAP") including a TAP CPU receiving target CPU input signals and delivering target CPU output signals for controlling the execution of software code on the target computer system in accordance with command signals provided by a host analysis code source, the TAP including a connector for electrically connecting the TAP CPU to the target computer system at the target CPU position, the TAP further including a memory storing an in-circuit emulation ("ICE") program containing instructions for the TAP CPU in accordance with the command signals from the host analysis code source, the ICE program residing wholly within the memory and outside both the target computer system and the target computer address space during execution of the ICE program by the TAP CPU, the TAP further including a TAP signal routing integrated circuit for assembling the host command signals into a digital word format and routing the assembled command signals to the TAP CPU; a communications adapter that provides an interface between the host analysis code source and the TAP; and a data communication link for providing a data communication link between the TAP and the communications adapter.
Claim 15
Dependent Claim
42 words
The instrument of claim 12 wherein the connector is fixedly mounted on the TAP and is adapted to plug directly into the target computer system at the target CPU position so that the TAP is physically supported by the target computer system.
Claim 16
Dependent Claim
44 words
The instrument of claim 12 wherein the TAP CPU includes emulation specific circuitry specially adapted to perform emulation functions, and wherein the emulation specific circuitry of the TAP CPU is accessible externally of the TAP CPU and coupled to other circuitry on the TAP.
Claim 17
Dependent Claim
18 words
The instrument of claim 12 wherein the communications adapter is physically separate from the host analysis code source.
Claim 18
Dependent Claim
31 words
The instrument of claim 12 wherein the TAP CPU further performs the function of communicating directly with the communications adapter to receive the command signals from the host analysis code source.
Claim 19
Dependent Claim
20 words
The instrument of claim 12 wherein the TAP CPU fetches the instructions of the ICE program directly from the memory.
Claim 20
Dependent Claim
24 words
The instrument of claim 12 wherein the TAP CPU is adapted to communicate with both the host analysis code source and the target CPU.
Claim 21
Dependent Claim
23 words
The instrument of claim 12 wherein the instructions of the ICE program are loaded into the memory upon initialization of the TAP CPU.
Claim 22
Dependent Claim
22 words
The instrument of claim 19 wherein all of the instructions of the ICE program are loaded upon initialization of the TAP CPU.
Claim 23
Dependent Claim
20 words
The instrument of claim 19 wherein multiple instructions of the ICE program are loaded upon initialization of the TAP CPU.
Claim 24
Dependent Claim
195 words
A target access probe ("TAP") for verifying and controlling the operational performance of software in a target system having a microprocessor position in accordance with instructions from a host analysis code source, comprising: a first connector for electrically and mechanically connecting the TAP to the target system at the target microprocessor position, the first connector being fixedly mounted on the TAP and being adapted for attachment directly to the target system so that the TAP is physically supported by the target system; a TAP microprocessor adapted to receive and transmit signals to and from the target system through the first connector; emulation circuitry adapted to store an in-circuit emulation ("ICE") program and provide instructions to the TAP microprocessor in accordance with instructions from the host analysis code source, the ICE program being stored entirely in the emulation circuitry on the TAP during execution of the ICE program by the TAP microprocessor so that the TAP microprocessor need not fetch instructions from the target system, the target system address space, or the host analysis source code during execution of the ICE program; and a second connector for linking the TAP with the host analysis code source.
Claim 25
Dependent Claim
195 words
A target access probe ("TAP") for verifying and controlling the operational performance of software in a target system having a microprocessor position in accordance with instructions from a host analysis code source, comprising: a first connector for electrically and mechanically connecting the TAP to the target system at the target microprocessor position, the first connector being fixedly mounted on the TAP and being adapted for attachment directly to the target system so that the TAP is physically supported by the target system; a TAP microprocessor adapted to receive and transmit signals to and from the target system through the first connector; emulation circuitry adapted to store an in-circuit emulation ("ICE") program and provide instructions to the TAP microprocessor in accordance with instructions from the host analysis code source, the ICE program being stored entirely in the emulation circuitry on the TAP during execution of the ICE program by the TAP microprocessor so that the TAP microprocessor need not fetch instructions from the target system, the target system address space, or the host analysis source code during execution of the ICE program; and a second connector for linking the TAP with the host analysis code source.
Claim 26
Dependent Claim
23 words
The TAP of claim 22 in which the ICE program is loaded into the emulation circuitry when power is applied to the TAP.
Claim 27
Dependent Claim
21 words
The TAP of claim 23 in which the ICE program is loaded into the emulation circuitry from outside of the TAP.
Claim 28
Dependent Claim
14 words
The TAP of claim 22 in which emulation circuitry comprises a random access memory.
Claim 29
Dependent Claim
44 words
The TAP of claim 22 wherein the TAP microprocessor includes emulation specific circuitry specially adapted to perform emulation functions, and wherein the emulation specific circuitry of the TAP microprocessor is accessible externally of the TAP microprocessor and coupled to other circuitry on the TAP.
Claim 30
Dependent Claim
32 words
The TAP of claim 22 wherein the TAP microprocessor further performs the function of communicating directly with the host analysis code source to receive the instructions from the host analysis code source.
Claim 31
Dependent Claim
35 words
The TAP of claim 22 wherein emulation circuitry includes a random access memory containing the ICE program, and wherein the TAP CPU fetches the instructions of the ICE program directly from the random access memory.
Claim 32
Dependent Claim
22 words
The TAP of claim 22 wherein the TAP CPU is adapted to communicate with both the host computer and the target CPU.
Claim 33
Dependent Claim
26 words
The TAP of claim 22 wherein the emulation circuitry includes a memory into which instructions of the ICE program are loaded upon initialization of the TAP.
Claim 34
Dependent Claim
21 words
The TAP of claim 30 wherein all of the instructions of the ICE program are loaded upon initialization of the TAP.
Claim 35
Dependent Claim
27 words
The TAP of claim 22 further comprising a signal routing integrated circuit for configuring electrical signals for transmission between the TAP and the host analysis code source.
Claim 36
Dependent Claim
17 words
The TAP of claim 32 in which the signal routing integrated circuit is of a programmable type.
Claim 37
Dependent Claim
43 words
The TAP of claim 32 in which instructions for programming the signal routing integrated circuit and the ICE program are loaded into the signal routing integrated circuit and the emulation circuitry, respectively, from outside the TAP upon application of power to the TAP.
Claim 38
Dependent Claim
17 words
The TAP of claim 32 in which the signal routing integrated circuit is of a reprogrammable type.
Claim 39
Dependent Claim
24 words
The TAP of claim 35 in which the signal routing integrated circuit is programmed by instructions received after application of power to the TAP.
Claim 40
Dependent Claim
22 words
The TAP of claim 36 in which the signal routing integrated circuit is programmed by instrructions received from outside of the TAP.
Claim 41
Dependent Claim
50 words
The TAP of claim 35 in which the TAP microprocessor includes a program counter and in which upon application of power to the TAP the signal routing integrated circuit is programmed, the ICE program is loaded into the emulation circuitry, and the program counter is set to a restart vector.
Claim 42
Dependent Claim
40 words
The TAP of claim 34 in which the TAP microprocessor includes BREAK and RESET conductors having logic states and in which the BREAK and RESET conductors are set to logic states of reset the program counter to a restart vector.
Claim 43
Dependent Claim
55 words
The TAP of claim 39 in which the TAP microprocessor includes CPU registers and in which the RESET conductor and BREAK conductor are set to logic states to dump the contents of the CPU register and the BREAK conductor is then set to a logic state to run the ICE program in the emulation circuitry.
Claim 44
Dependent Claim
226 words
An instrument for testing and verifying the operational performance of software in a target computer system in the electrical absence of a target CPU having input and output terminal positions at which respective specified target CPU input and output signals appear, the instrument comprising: a target access probe ("TAP") including a connector for electrically and mechanically connecting the TAP to the target system at the target CPU position, the connector being fixedly mounted on the TAP and being adapted for attachment directly to the target computer system so that the TAP is physically supported by the target computer system; a TAP microprocessor adapted to receive and transmit signals to and from the target computer system; emulation circuitry adapted to store an in-circuit emulation ("ICE") program that resides wholly within the emulation circuitry and outside of the target computer system and target computer system address space during execution of the ICE program to provide instructions to the TAP microprocessor so that tile TAP itself can function as an emulator in accordance with instructions from a host analysis code source; the microprocessor and emulation circuitry being mounted in a common chassis; and a communications adapter operatively connected to and cooperating with the TAP to provide an interface between the host analysis code source and the TAP to route signals between the TAP and the host analysis code source.
Claim 45
Dependent Claim
226 words
An instrument for testing and verifying the operational performance of software in a target computer system in the electrical absence of a target CPU having input and output terminal positions at which respective specified target CPU input and output signals appear, the instrument comprising: a target access probe ("TAP") including a connector for electrically and mechanically connecting the TAP to the target system at the target CPU position, the connector being fixedly mounted on the TAP and being adapted for attachment directly to the target computer system so that the TAP is physically supported by the target computer system; a TAP microprocessor adapted to receive and transmit signals to and from the target computer system; emulation circuitry adapted to store an in-circuit emulation ("ICE") program that resides wholly within the emulation circuitry and outside of the target computer system and target computer system address space during execution of the ICE program to provide instructions to the TAP microprocessor so that tile TAP itself can function as an emulator in accordance with instructions from a host analysis code source; the microprocessor and emulation circuitry being mounted in a common chassis; and a communications adapter operatively connected to and cooperating with the TAP to provide an interface between the host analysis code source and the TAP to route signals between the TAP and the host analysis code source.
Claim 46
Dependent Claim
36 words
The instrument of claim 41 in which the communications adapter includes a memory storing the ICE program and in which the ICE program is loaded into the emulation circuitry upon application of power to the instrument.
Claim 47
Dependent Claim
39 words
The instrument of claim 41 in which the TAP further includes a signal routing integrated circuit for configuring signal paths within the TAP and the communications adapter includes a memory storing information for configuring the signal routing integrated circuit.
Claim 48
Dependent Claim
19 words
The instrument of claim 41 in which the communications adapter is physically separate from the host analysis code source.
Claim 49
Dependent Claim
16 words
The instrument of claim 41 in which the communications adapter is physically separate from the TAP.
Claim 50
Dependent Claim
41 words
The instrument of claim 41 wherein the connector is fixedly mounted on the chassis and is adapted to plug directly into the target system at the target CPU position so that the TAP chassis is physically supported by the target system.
Claim 51
Dependent Claim
44 words
The instrument of claim 41 wherein the TAP microprocessor includes emulation specific circuitry specially adapted to perform emulation functions, and wherein the emulation specific circuitry of the TAP microprocessor is accessible externally of the TAP microprocessor and coupled to other circuitry on the TAP.
Claim 52
Dependent Claim
18 words
The instrument of claim 41 wherein the communications adapter is physically separate from the host analysis code source.
Claim 53
Dependent Claim
30 words
The instrument of claim 41 wherein the TAP microprocessor further performs the function of communicating directly with the communications adapter to receive the instructions from the host analysis code source.
Claim 54
Dependent Claim
21 words
The instrument of claim 41 wherein the TAP CPU fetches the instructions of the ICE program directly from the emulation circuitry.
Claim 55
Dependent Claim
24 words
The instrument of claim 41 wherein the TAP CPU is adapted to communicate with both the host analysis code source and the target CPU.
Claim 56
Dependent Claim
24 words
The instrument of claim 41 wherein the instructions of the ICE program are loaded into the emulation circuitry upon initialization of the TAP CPU.
Claim 57
Dependent Claim
22 words
The instrument of claim 52 wherein all of the instructions of the ICE program are loaded upon initialization of the TAP CPU.
Claim 58
Dependent Claim
20 words
The instrument of claim 52 wherein multiple instructions of the ICE program are loaded upon initialization of the TAP CPU.
Claim 59
Dependent Claim
67 words
The instrument of claim 41 in which the tap further includes a reprogrammable signal routing integrated circuit for configuring electrical signals for transmission between the TAP and the host analysis code source communications adapter by way of the communications adapter and in which the communications adapter includes a memory storing configuration information that is loaded into the logic cell array upon application of power to the instrument.
Claim 60
Independent Claim
141 words
A method of configuring a target access probe ("TAP") connected to a microprocessor position of a target system and including a TAP microprocessor, in-circuit emulation ("ICE") circuitry, a TAP signal routing integrated circuit, and a signal link connecting the TAP to a host system, the method comprising: applying electrical power to the TAP; configuring the TAP signal routing integrated circuit by applying signals through the signal link to the signal routing integrated circuit; loading an ICE program into the ICE circuitry by downloading the program through the signal link and the signal routing integrated circuit after the signal routing integrated circuit has been configured; and the ICE program being stored entirely in the ICE circuitry on the TAP during execution of the ICE program by the TAP microprocessor allowing the TAP microprocessor to execute the ICE program from the ICE circuitry.
Claim 61
Independent Claim
141 words
A method of configuring a target access probe ("TAP") connected to a microprocessor position of a target system and including a TAP microprocessor, in-circuit emulation ("ICE") circuitry, a TAP signal routing integrated circuit, and a signal link connecting the TAP to a host system, the method comprising: applying electrical power to the TAP; configuring the TAP signal routing integrated circuit by applying signals through the signal link to the signal routing integrated circuit; loading an ICE program into the ICE circuitry by downloading the program through the signal link and the signal routing integrated circuit after the signal routing integrated circuit has been configured; and the ICE program being stored entirely in the ICE circuitry on the TAP during execution of the ICE program by the TAP microprocessor allowing the TAP microprocessor to execute the ICE program from the ICE circuitry.
Claim 62
Dependent Claim
40 words
The method of claim 56 in which the TAP microprocessor includes a program counter and registers and further comprising: setting program counter to a reset vector; writing the contents of CPU registers to another memory; and running an ICE program.
Claim 63
Dependent Claim
47 words
The method of claim 56 in which the TAP communicates with the host analysis source code through a communications adapter and in which downloading the ICE program includes transferring the ICE program from the communications adapter to the ICE circuitry through the TAP signal routing integrated circuit.
Claim 64
Dependent Claim
39 words
The method of claim 56 further including the step of maintaining the TAP microprocessor, in a reset condition while the ICE program is being loaded into the ICE circuitry through the signal link and the signal routing integrated circuit.
Claim 65
Dependent Claim
34 words
The method of claim 56 wherein multiple instruction bytes of the ICE program are downloaded into the ICE circuitry upon configuring the TAP prior to execution of the ICE program by the TAP microprocessor.
Claim 66
Dependent Claim
31 words
The method of claim 56 wherein the entire ICE program is loaded into the ICE circuitry upon configuring the TAP prior to execution of the ICE program by the TAP microprocessor.
Claim 67
Dependent Claim
45 words
The method of claim 56 in which the TAP communicates with the host analysis source code through a communications adapter and in which configuring the TAP signal routing integrated circuit and loading an ICE program include transferring data to the TAP from the communications adapter.
Claim 68
Dependent Claim
44 words
The method of claim 62 in which the communications adapter includes a communications adapter signal routing integrated circuit and in which configuring the TAP signal routing integrated circuit and loading an ICE program include transferring data through the communications adapter signal routing integrated circuit.
Claim 69
Dependent Claim
41 words
The method of claim 63 in which the communications adapter signal routing integrated circuit is of a reprogrammable type and in which transferring data through the communications adapter signal routing integrated circuit includes configuring the communications adapter signal routing integrated circuit.
Claim 70
Dependent Claim
34 words
The method of claim 64 in which the communications adapter includes memory sites and in which data for configuring the communications adapter signal routing integrated circuit are stored in the communications adapter memory sites.
Claim 71
Dependent Claim
27 words
The method of claim 62 in which the communications adapter includes memory sites and in which the ICE program is stored in the communications adapter memory sites.
Claim 72
Dependent Claim
32 words
The method of claim 62 in which the communications adapter includes memory sites in which data for configuring the TAP signal routing integrated circuit is stored in the communications adapter memory sites.
Claim 73
Dependent Claim
262 words
An instrument for verifying and controlling the operational performance of software in a target computer system in the electrical absence of a target CPU having input and output terminal positions at which respective target CPU input and output signals appear, the instrument comprising: a user interface device generating command signals corresponding to manually selected user inputs; a target access probe including a probe CPU of the same type as the target CPU and an in-circuit emulation memory storing an in-circuit emulation program that resides wholly within the in-circuit emulation memory and outside of the target computer system and the target computer system address space during execution of the in-circuit emulation program by the probe CPU so that the probe CPU need not fetch instructions from the target system or the user interface device during execution of the in-circuit emulation program, thereby allowing the target access probe itself to a function as an emulator, the in-circuit emulation memory providing instructions to the probe CPU in accordance with the command signals from the user interface device; a signal link connecting the target access probe to the user interface device to allow the target access probe to receive the command signals from the user interface device; and a connector electrically and mechanically connecting terminals of the target access probe to corresponding input and output terminal positions of the target CPU, the connector being fixedly mounted on the target access probe and being adapted for attachment directly to the target computer system so that the target access probe is physically supported by the target computer system.
Claim 74
Dependent Claim
262 words
An instrument for verifying and controlling the operational performance of software in a target computer system in the electrical absence of a target CPU having input and output terminal positions at which respective target CPU input and output signals appear, the instrument comprising: a user interface device generating command signals corresponding to manually selected user inputs; a target access probe including a probe CPU of the same type as the target CPU and an in-circuit emulation memory storing an in-circuit emulation program that resides wholly within the in-circuit emulation memory and outside of the target computer system and the target computer system address space during execution of the in-circuit emulation program by the probe CPU so that the probe CPU need not fetch instructions from the target system or the user interface device during execution of the in-circuit emulation program, thereby allowing the target access probe itself to a function as an emulator, the in-circuit emulation memory providing instructions to the probe CPU in accordance with the command signals from the user interface device; a signal link connecting the target access probe to the user interface device to allow the target access probe to receive the command signals from the user interface device; and a connector electrically and mechanically connecting terminals of the target access probe to corresponding input and output terminal positions of the target CPU, the connector being fixedly mounted on the target access probe and being adapted for attachment directly to the target computer system so that the target access probe is physically supported by the target computer system.
Claim 75
Dependent Claim
54 words
The instrument of claim 68 wherein the target access probe further includes a programmable signal routing circuit that, after being programmed by the user interface device, routes the in-circuit emulation program from the user interface device and downloads the in-circuit emulation program into the in-circuit emulation memory prior to execution by the probe CPU.
Claim 76
Dependent Claim
36 words
The instrument of claim 68 wherein the signal link connecting the target access probe to the user interface includes a communications adapter to provide an interface between the user interface device and the target access probe.
Claim 77
Dependent Claim
17 words
The instrument of claim 70 wherein the communications adapter is physically separate from the user interface device.
Claim 78
Dependent Claim
31 words
The instrument of claim 70 wherein the probe CPU further performs the function of communicating directly with the communications adapter to receive the in-circuit emulation program from the user interface device.
Claim 79
Dependent Claim
46 words
The instrument of claim 68 wherein the connector is fixedly mounted on the target access probe and is adapted to plug directly into the target computer system at the target CPU position so that the target access probe is physically supported by the target computer system.
Claim 80
Dependent Claim
46 words
The instrument of claim 68 wherein the probe CPU includes emulation specific circuitry specially adapted to perform emulation functions, and wherein the emulation specific circuitry of the probe CPU is accessible externally of the probe CPU and coupled to other circuitry on the target access probe.
Claim 81
Dependent Claim
26 words
The instrument of claim 68 wherein the instructions of the in-circuit emulation program are loaded into the in-circuit emulation memory upon initialization of the probe CPU.
Claim 82
Dependent Claim
28 words
The instrument of claim 75 wherein all of the instructions of the in-circuit emulation program are loaded into the in-circuit emulation memory upon initialization of the probe CPU.
Claim 83
Dependent Claim
26 words
The instrument of claim 75 wherein multiple instructions of the in-circuit emulation program are loaded into the in-circuit emulation memory upon initialization of the probe CPU.
Claim 84
Dependent Claim
22 words
The instrument of claim 68 wherein the probe CPU fetches instructions of the in-circuit emulation program directly from the in-circuit emulation memory.
Claim 85
Dependent Claim
23 words
The instrument of claim 68 wherein the probe CPU is adapted to communicate with both the user interface device and the target CPU.
Claim 86
Independent Claim
119 words
A method of configuring a target access probe ("TAP") connected to a microprocessor position of a target system and including a TAP microprocessor, in-circuit emulation ("ICE") circuitry, a TAP signal routing integrated circuit, and a signal link connecting the TAP to a host system, the method comprising: applying electrical power to the TAP; configuring the TAP signal routing integrated circuit; loading an ICE program into the ICE circuitry by downloading the program through the signal link and the signal routing integrated circuit; and the ICE program being stored entirely in the ICE circuitry on the TAP during execution of the ICE program by the TAP microprocessor allowing the TAP microprocessor to execute the ICE program from the ICE circuitry.
Claim 87
Independent Claim
119 words
A method of configuring a target access probe ("TAP") connected to a microprocessor position of a target system and including a TAP microprocessor, in-circuit emulation ("ICE") circuitry, a TAP signal routing integrated circuit, and a signal link connecting the TAP to a host system, the method comprising: applying electrical power to the TAP; configuring the TAP signal routing integrated circuit; loading an ICE program into the ICE circuitry by downloading the program through the signal link and the signal routing integrated circuit; and the ICE program being stored entirely in the ICE circuitry on the TAP during execution of the ICE program by the TAP microprocessor allowing the TAP microprocessor to execute the ICE program from the ICE circuitry.
Claim 88
Dependent Claim
29 words
The method of claim 80 further including the step of holding the TAP microprocessor in a reset condition while the ICE program is being loaded into the ICE circuitry.
Claim 89
Dependent Claim
47 words
The method of claim 80 in which the TAP communicates with a host analysis source code through a communications adapter and in which downloading the ICE program includes transferring the ICE program from the communications adapter to the ICE circuitry through the TAP signal routing integrated circuit.
Claim 90
Dependent Claim
36 words
The method of claim 80 wherein multiple instructions of the ICE program are downloaded into the ICE circuitry upon configuring the TAP prior to execution of the ICE program by the microprocessor of the target system.
Claim 91
Dependent Claim
34 words
The method of claim 80 wherein the entire ICE program is downloaded into the ICE circuitry upon configuring the TAP prior to execution of the ICE program by the microprocessor of the target system.
Claim 92
Independent Claim
128 words
A method of configuring a target access probe ("TAP") connected to a microprocessor position of a target system and including a TAP microprocessor, in-circuit emulation ("ICE") circuitry, a TAP signal routing integrated circuit, and a signal link connecting the TAP to a host system, the method comprising: applying electrical power to the TAP; configuring the TAP signal routing integrated circuit by applying signals to the signal routing integrated circuit; loading an ICE program into the ICE circuitry by downloading the program through the signal link and the signal routing integrated circuit; and the ICE program being stored entirely in the ICE circuitry on the TAP during execution of the ICE program by the TAP microprocessor allowing the TAP microprocessor to execute the ICE program from the ICE circuitry.
Claim 93
Independent Claim
128 words
A method of configuring a target access probe ("TAP") connected to a microprocessor position of a target system and including a TAP microprocessor, in-circuit emulation ("ICE") circuitry, a TAP signal routing integrated circuit, and a signal link connecting the TAP to a host system, the method comprising: applying electrical power to the TAP; configuring the TAP signal routing integrated circuit by applying signals to the signal routing integrated circuit; loading an ICE program into the ICE circuitry by downloading the program through the signal link and the signal routing integrated circuit; and the ICE program being stored entirely in the ICE circuitry on the TAP during execution of the ICE program by the TAP microprocessor allowing the TAP microprocessor to execute the ICE program from the ICE circuitry.
Claim 94
Dependent Claim
47 words
The method of claim 85 in which the TAP communicates with a host analysis source code through a communications adapter and in which downloading the ICE program includes transferring the ICE program from the communications adapter to the ICE circuitry through the TAP signal routing integrated circuit.
Claim 95
Dependent Claim
45 words
The method of claim 85 in which the TAP communicates with the host analysis source code through a communications adapter and in which configuring the TAP signal routing integrated circuit and loading an ICE program include transferring data to the TAP from the communications adapter.
Claim 96
Dependent Claim
29 words
The method of claim 85 further including the step of holding the TAP microprocessor in a reset condition while the ICE program is being loaded into the ICE circuitry.
Claim 97
Dependent Claim
33 words
The method of claim 85 wherein multiple instructions of the ICE program are downloaded into the ICE circuitry upon configuring the TAP prior to execution of the ICE program by the TAP microprocessor.
Claim 98
Dependent Claim
31 words
The method of claim 85 wherein the entire ICE program is downloaded into the ICE circuitry upon configuring the TAP prior to execution of the ICE program by the TAP microprocessor.
Claim 99
Dependent Claim
242 words
An instrument for verifying and controlling the operational performance of software in a target computer system in the electrical absence of a target CPU having input and output terminal positions at which respective target CPU input and output signals appear, the instrument comprising: a user interface device generating command signals corresponding to manually selected user inputs; a target access probe including a probe CPU of the same type as the target CPU, an in-circuit emulation memory storing an in-circuit emulation program that resides wholly within the in-circuit emulation memory and outside of the target computer system and the target computer system address space during execution of the in-circuit emulation program by the probe CPU so that the probe CPU need not fetch instructions from the target system or the user interface device during execution of the in-circuit emulation program, thereby allowing the target access probe itself to a function as an emulator, the in-circuit memory providing instructions to the probe CPU in accordance with the command signals from the user interface device, the target access probe further including a signal routing integrated circuit for routing signals in the target access probe; a signal link connecting the target access probe to the user interface device to allow the target access probe to receive the command signals from the user interface device; and a connector electrically connecting terminals of the target access probe to corresponding input and output terminal positions of the target CPU.
Claim 100
Dependent Claim
242 words
An instrument for verifying and controlling the operational performance of software in a target computer system in the electrical absence of a target CPU having input and output terminal positions at which respective target CPU input and output signals appear, the instrument comprising: a user interface device generating command signals corresponding to manually selected user inputs; a target access probe including a probe CPU of the same type as the target CPU, an in-circuit emulation memory storing an in-circuit emulation program that resides wholly within the in-circuit emulation memory and outside of the target computer system and the target computer system address space during execution of the in-circuit emulation program by the probe CPU so that the probe CPU need not fetch instructions from the target system or the user interface device during execution of the in-circuit emulation program, thereby allowing the target access probe itself to a function as an emulator, the in-circuit memory providing instructions to the probe CPU in accordance with the command signals from the user interface device, the target access probe further including a signal routing integrated circuit for routing signals in the target access probe; a signal link connecting the target access probe to the user interface device to allow the target access probe to receive the command signals from the user interface device; and a connector electrically connecting terminals of the target access probe to corresponding input and output terminal positions of the target CPU.
Claim 101
Dependent Claim
22 words
The instrument of claim 91 wherein the probe CPU fetches instructions of the in-circuit emulation program directly from the in-circuit emulation memory.
Claim 102
Dependent Claim
23 words
The instrument of claim 91 wherein the probe CPU is adapted to communicate with both the user interface device and the target CPU.
Claim 103
Dependent Claim
24 words
The instrument of claim 91 wherein the in-circuit emulation program is loaded into the in-circuit emulation memory upon initialization of the target access probe.
Claim 104
Dependent Claim
24 words
The instrument of claim 94 wherein all of the instructions of the in-circuit emulation program are loaded upon initialization of the target access probe.
Claim 105
Dependent Claim
22 words
The instrument of claim 94 wherein multiple instructions of the in-circuit emulation program are loaded upon initialization of the target access probe.
Claim 106
Dependent Claim
41 words
The instrument of claim 96 wherein the connector is fixedly mounted on the target access probe and is adapted for attachment directly to the target computer system so that the target access probe is physically supported by the target computer system.
Claim 107
Dependent Claim
192 words
An instrument for testing and verifying the operational performance of software in a target computer system in the electrical absence of a target CPU having input and output terminal positions at which respective specified target CPU input and output signals appear, the instrument comprising: a target access probe ("TAP") including a connector for electrically connecting the TAP to the target system at the target CPU position; a TAP microprocessor adapted to receive and transmit signals to and from the target system; emulation circuitry adapted to store an in-circuit emulation ("ICE") program that resides wholly within the emulation circuitry and outside of the target system and target system address space during execution of the ICE program to provide instructions to the TAP microprocessor so that the TAP itself can function as an emulator in accordance with instructions from a host analysis code source; and a TAP signal routing integrated circuit for routing signals in the TAP; and a communications adapter operatively connected to and cooperating with the TAP to provide an interface between the host analysis code source and the TAP to route signals between the TAP and the host analysis code source.
Claim 108
Dependent Claim
192 words
An instrument for testing and verifying the operational performance of software in a target computer system in the electrical absence of a target CPU having input and output terminal positions at which respective specified target CPU input and output signals appear, the instrument comprising: a target access probe ("TAP") including a connector for electrically connecting the TAP to the target system at the target CPU position; a TAP microprocessor adapted to receive and transmit signals to and from the target system; emulation circuitry adapted to store an in-circuit emulation ("ICE") program that resides wholly within the emulation circuitry and outside of the target system and target system address space during execution of the ICE program to provide instructions to the TAP microprocessor so that the TAP itself can function as an emulator in accordance with instructions from a host analysis code source; and a TAP signal routing integrated circuit for routing signals in the TAP; and a communications adapter operatively connected to and cooperating with the TAP to provide an interface between the host analysis code source and the TAP to route signals between the TAP and the host analysis code source.
Claim 109
Dependent Claim
24 words
The instrument of claim 98 wherein the instructions of the ICE program are loaded into the emulation circuitry upon initialization of the TAP CPU.
Claim 110
Dependent Claim
22 words
The instrument of claim 99 wherein all of the instructions of the ICE program are loaded upon initialization of the TAP CPU.
Claim 111
Dependent Claim
20 words
The instrument of claim 99 wherein multiple instructions of the ICE program are loaded upon initialization of the TAP CPU.
Claim 112
Dependent Claim
21 words
The instrument of claim 98 wherein the TAP CPU fetches the instructions of the ICE program directly from the emulation circuitry.
Claim 113
Dependent Claim
24 words
The instrument of claim 98 wherein the TAP CPU is adapted to communicate with both the host analysis code source and the target CPU.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-12-03 | 2000-06-03 | 2000-12-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-12-03 | 2004-06-03 | 2004-12-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-12-03 | 2008-06-03 | 2008-12-03 | $7700.00 | Window Closed / Lapsed |