Hardware enhancements for improved performance of memory emulation method

Claim 3

The apparatus according to claim 1, wherein said gated data buffer means and said gated status buffer means are coupled to said microprocessor by coupling means including respective conductor means in a common cable.

Claim 4

The apparatus according to claim 2, wherein said coupling means includes a respective buffer means for each said conductor means.

Claim 5

The apparatus according to claim 3, further including a test system evaluation means for evaluating signals captured by said test apparatus and wherein said output means includes means for coupling at least said gated data buffer means to an input of said test system evaluation means.

Claim 6

The apparatus according to claim 4, wherein said test system evaluation means is a microprocessor.

Claim 7

An arrangement for calibrating a memory evaluation test apparatus which tests a microprocessor-based unit under test (UUT) having a kernel formed by at least a microprocessor, a memory and a data bus and an address bus, said arrangement comprising: emulation memory means connectable to said UUT in substitution for said UUT memory during calibration of said testing apparatus, means for loading a selected bit pattern into a predetermined location in said emulation memory means, means for causing said microprocessor to access said preselected location of said emulation memory whereby said emulation memory is caused to place said preselected bit pattern on said data bus, synchronization signal generation means including means for comparing signal bits appearing on said data bus with bits of said preselected bit pattern and bus cycle counting means for counting bus cycles prior to when said comparison means detects a bit pattern on said data bus matching said bits of said preselected bit pattern, and means for producing a synchronization signal a number of bus cycles after further access of said emulation memory equal to the number of bus cycles counted by said counting means.

Claim 8

An arrangement for calibrating a memory evaluation test apparatus which tests a microprocessor-based unit under test (UUT) having a kernel formed by at least a microprocessor, a memory and a data bus and an address bus, said arrangement comprising: emulation memory means connectable to said UUT in substitution for said UUT memory during calibration of said testing apparatus, means for loading a selected bit pattern into a predetermined location in said emulation memory means, means for causing said microprocessor to access said preselected location of said emulation memory whereby said emulation memory is caused to place said preselected bit pattern on said data bus, synchronization signal generation means including means for comparing signal bits appearing on said data bus with bits of said preselected bit pattern and bus cycle counting means for counting bus cycles prior to when said comparison means detects a bit pattern on said data bus matching said bits of said preselected bit pattern, and means for producing a synchronization signal a number of bus cycles after further access of said emulation memory equal to the number of bus cycles counted by said counting means.

Claim 11

Apparatus for testing, by memory emulation, a microprocessor-based unit under test (UUT) having a kernel formed by at least a microprocessor and a memory, comprising: an emulation memory for connection to said UUT in substitution for said UUT memory during testing of said UUT; first connection means for connecting said emulation memory to said system; second connection means for connecting said apparatus to at least one status pin and one data input pin of said microprocessor; means for reading data from said emulation memory under control of said UUT microprocessor; and a self-test circuit means, comprising: (a) a gated buffer circuit means including a gated data buffer circuit means and a gated status buffer circuit means, (b) connector means for connecting said first connection means and said second connection means to an input/output port of said apparatus, and (c) means for reading data stored in said gated buffer circuit means to self-test said apparatus.

Claim 12

Apparatus for testing, by memory emulation, a microprocessor-based unit under test (UUT) having a kernel formed by at least a microprocessor and a memory, comprising: an emulation memory for connection to said UUT in substitution for said UUT memory during testing of said UUT; first connection means for connecting said emulation memory to said system; second connection means for connecting said apparatus to at least one status pin and one data input pin of said microprocessor; means for reading data from said emulation memory under control of said UUT microprocessor; and a self-test circuit means, comprising: (a) a gated buffer circuit means including a gated data buffer circuit means and a gated status buffer circuit means, (b) connector means for connecting said first connection means and said second connection means to an input/output port of said apparatus, and (c) means for reading data stored in said gated buffer circuit means to self-test said apparatus.

Claim 13

An adaptive synchronization signal generating circuit for use in a tester for microprocessor-based systems including a microprocessor, a memory and a memory access bus, said circuit including: means for causing a predetermined bit pattern to be read from said memory and placed on said memory access but at a predetermined time, means for monitoring said memory access bus to detect an occurrence of said predetermined bit pattern, means for counting processing cycles of said microprocessor between said predetermined time and detection of said predetermined bit pattern by said means for monitoring said memory access bus, and means for storing a count produced by said means for counting processing cycles of said microprocessor.

Claim 14

An adaptive synchronization signal generating circuit for use in a tester for microprocessor-based systems including a microprocessor, a memory and a memory access bus, said circuit including: means for causing a predetermined bit pattern to be read from said memory and placed on said memory access but at a predetermined time, means for monitoring said memory access bus to detect an occurrence of said predetermined bit pattern, means for counting processing cycles of said microprocessor between said predetermined time and detection of said predetermined bit pattern by said means for monitoring said memory access bus, and means for storing a count produced by said means for counting processing cycles of said microprocessor.

Claim 15

An adaptive synchronization signal generating circuit for use in a tester for microprocessor-based system as recited in claim 9, further including: means for causing a second predetermined bit pattern to be read from said memory and placed on said memory access but at a predetermined time, and means for updating storage by said means for storing of said processing cycle count by said means for counting processing cycles of said microprocessor based on a count of processing cycles between said second predetermined bit pattern being read from said memory and detection of said second predetermined bit pattern on said memory access bus.

Claim 16

An adaptive synchronization signal generating method for use in a tester for microprocessor-based systems including a microprocessor, a memory and a memory access bus, including the steps of: causing a predetermined bit pattern to be read from said memory and placed on said memory access bus at a predetermined time, monitoring said memory access bus to detect an occurrence of said predetermined bit pattern, counting processing cycles of said microprocessor between said predetermined time and detection of said predetermined bit pattern, and storing said count of processing cycles of said microprocessor between said predetermined time and detection of said predetermined bit pattern.

Claim 17

An adaptive synchronization signal generating method for use in a tester for microprocessor-based systems including a microprocessor, a memory and a memory access bus, including the steps of: causing a predetermined bit pattern to be read from said memory and placed on said memory access bus at a predetermined time, monitoring said memory access bus to detect an occurrence of said predetermined bit pattern, counting processing cycles of said microprocessor between said predetermined time and detection of said predetermined bit pattern, and storing said count of processing cycles of said microprocessor between said predetermined time and detection of said predetermined bit pattern.

Claim 18

An adaptive synchronization signal generating method for use in a tester for microprocessor-based systems as recited in claim 11, further including steps of causing a second predetermined bit pattern to be read from said memory and placed on said memory access bus at a predetermined time, and updating storage of said processing cycle count based on a count of processing cycles between said second predetermined bit pattern being read from said memory and detection of said second predetermined bit pattern on said memory access bus.