US4683568A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of monitoring computer elements, particularly microprocessors
Assignee: Robert Bosch GmbH
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Filing: 1984-11-02
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Granted: 1987-07-28
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Expires: 2004-11-02
Abstract
Abstract A method is proposed which serves to enable recognition, in microprocessors (1) provided with a monitoring device (2) having a signal generator stage for reset signals, of whether a reset signal was effected by the monitoring device (2) or by a power-on reset circuit (5). To this end, a comparison is performed between a comparison pattern stored in a non-erasable memory zone (6) and a pattern, which is typical of resetting erected by the monitoring device (2), located in an erasable memory zone (7).
Inventors
- 👤 Manfred Urban
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 20:43
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/14; G06F11/1402; G06F11/1415
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
9 words
Method for monitoring computer elements (1), particularly microprocessors, having
Claim 2
Dependent Claim
9 words
Method for monitoring computer elements (1), particularly microprocessors, having
Claim 3
Dependent Claim
4 words
a reset input (12),
Claim 4
Dependent Claim
4 words
a reset input (12),
Claim 5
Dependent Claim
6 words
a volatile or eraseable memory (7),
Claim 6
Dependent Claim
6 words
a volatile or eraseable memory (7),
Claim 7
Dependent Claim
6 words
a non-volatile or non-eraseable memory (6),
Claim 8
Dependent Claim
6 words
a non-volatile or non-eraseable memory (6),
Claim 9
Dependent Claim
103 words
input/output port means (13) connecting said memories to the computer element (1), a monitoring device (2) for the computer element (1) which device causes a resetting of the computer element (1), comprising the steps of detecting a reset signal on said reset input (12), performing a comparison (62) between a comparison pattern stored in said non-eraseable memory (6) and a pattern present in said eraseable memory (7); and performing, selectively, one of a complete re-initialization (65) of said microprocessor and a shorter program sequence (64) in dependence upon whether said comparison indicates that the pattern in said volatile or eraseable memory is random.
Claim 10
Dependent Claim
103 words
input/output port means (13) connecting said memories to the computer element (1), a monitoring device (2) for the computer element (1) which device causes a resetting of the computer element (1), comprising the steps of detecting a reset signal on said reset input (12), performing a comparison (62) between a comparison pattern stored in said non-eraseable memory (6) and a pattern present in said eraseable memory (7); and performing, selectively, one of a complete re-initialization (65) of said microprocessor and a shorter program sequence (64) in dependence upon whether said comparison indicates that the pattern in said volatile or eraseable memory is random.
Claim 11
Dependent Claim
42 words
Method according to claim 1, characterized in that if there is at least partial equality between the pattern and the comparison pattern, a program (64) is carried out which executes a function associated with a reset caused by the monitoriing device (2).
Claim 12
Dependent Claim
18 words
Method according to claim 2, characterized in that the function includes an activation of the monitoring device (2).
Claim 13
Dependent Claim
116 words
Computer apparatus, for performing a method according to any one of the foregoing claims, having said reset input (12), said monitoring device (2) for the computer element (1) which device causes a resetting of the computer element (1), said volatile or eraseable memory (7), said non-volatile or non-eraseable memory (6), said input/output port means (13) connecting said memories to the computer element (1), a power-on circuit (5), and a logical linking device (4), wherein both the monitoring device (2) and the power-on reset circuit (5) are connected to inputs of said logical linking element (4), and the output of the logical linking element (4) is connected to said reset input (12) of the computer element (1).
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-07-27 | 1991-01-26 | 1991-07-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-07-27 | 1995-01-26 | 1995-07-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-07-27 | 1999-01-26 | 1999-07-28 | $7700.00 | Window Closed / Lapsed |