Gate insulated semiconductor device

Claim 2

A semiconductor device comprising: a substrate having an insulating surface; a semiconductor layer formed on said insulating surface, said semiconductor layer comprising a first region, at least one second region and a pair of third regions, said first region functioning as a channel and said pair of third regions functioning as source and drain regions; a gate insulating layer located adjacent to said semiconductor layer; and a gate electrode located adjacent to said gate insulating layer, wherein said first and second regions extend between said pair of third regions and said at least one second region extends between said first region and at least one of said third regions, and wherein a total concentration of oxygen, carbon and nitrogen in said at least one second region is higher than a total concentration of oxygen, carbon and nitrogen in said first region.

Claim 3

The semiconductor device of claim 1 wherein said semiconductor layer is crystalline.

Claim 4

The semiconductor device of claim 1 wherein the total concentration of oxygen, carbon and nitrogen in said at least one second region is the same as a total concentration of oxygen, carbon and nitrogen in said pair of third regions.

Claim 5

The semiconductor device of claim 1 wherein said gate electrode is provided with an anodic oxide thereof on its surface.

Claim 6

The semiconductor device of claim 1 wherein said semiconductor layer comprises silicon.

Claim 7

The semiconductor device of claim 5 wherein said source and drain regions comprise a metal silicide.

Claim 8

The semiconductor device of claim 6 wherein said metal silicide contains a metal selected from the group consisting of titanium, tungsten, platinum, palladium and nickel.

Claim 9

The semiconductor device of claim 1 wherein said semiconductor layer contains a crystallization promoting metal element.

Claim 10

The semiconductor device of claim 4 wherein each boundary between said at least one second region and said pair of third regions is aligned with an outer edge of said anodic oxide.

Claim 11

The semiconductor device of claim 1 wherein said pair of third regions is doped with one conductivity type impurity at a first concentration.

Claim 12

The semiconductor device of claim 10 wherein said at least one second region is doped with said one conductivity type impurity at a second concentration which is smaller than said first concentration.

Claim 13

A semiconductor device comprising: a substrate having an insulating surface; a semiconductor layer formed on said insulating surface, said semiconductor layer comprising a first region, a pair of second regions between which said first region extends, and a pair of third regions between which said first and second regions extend; a gate insulating layer located adjacent to the first region of said semiconductor layer; a pair of metal silicide layers contacting said pair of third regions; and a gate electrode located adjacent to said gate insulating layer, wherein said first region and said pair of second regions have an intrinsic or substantially intrinsic conductivity type, said pair of third regions are doped with one conductivity type impurity and have one conductivity type, a concentration of carbon, oxygen or nitrogen contained in said pairs of second and third regions is higher than that in said first region.

Claim 14

A semiconductor device comprising: a substrate having an insulating surface; a semiconductor layer formed on said insulating surface, said semiconductor layer comprising a first region, a pair of second regions between which said first region extends, and a pair of third regions between which said first and second regions extend; a gate insulating layer located adjacent to the first region of said semiconductor layer; a pair of metal silicide layers contacting said pair of third regions; and a gate electrode located adjacent to said gate insulating layer, wherein said first region and said pair of second regions have an intrinsic or substantially intrinsic conductivity type, said pair of third regions are doped with one conductivity type impurity and have one conductivity type, a concentration of carbon, oxygen or nitrogen contained in said pairs of second and third regions is higher than that in said first region.

Claim 15

The semiconductor device of claim 12 wherein said semiconductor layer is crystalline.

Claim 16

The semiconductor device of claim 12 wherein said metal silicide layers are doped with carbon, nitrogen or oxygen at the same concentration as said pair of third regions.

Claim 17

The semiconductor device of claim 12 wherein said gate electrode is provided with an anodic oxide thereof on its surface.

Claim 18

The semiconductor device of claim 12 wherein said semiconductor layer comprises silicon.

Claim 19

The semiconductor device of claim 12 wherein said pair of metal silicide layers are doped with said one conductivity type impurity at a concentration higher than that contained in said pair of third regions.

Claim 20

The semiconductor device of claim 12 wherein said pair of metal silicide layers contain a metal selected from the group consisting of titanium, tungsten, platinum, palladium and nickel.

Claim 21

The semiconductor device of claim 12 wherein said semiconductor layer contains a crystallization promoting metal element.

Claim 22

The semiconductor device of claim 15 wherein each boundary between said pair of second regions and said pair of third regions is aligned with an outer edge of said anodic oxide.

Claim 23

A thin film semiconductor integrated circuit comprising: a substrate having an insulating surface, said substrate having an active matrix circuit portion and a peripheral circuit portion; a plurality of electrodes formed in the active matrix circuit portion; a plurality of first thin film transistors connected to said electrodes in the active matrix circuit portion; a plurality of second thin film transistors formed in said peripheral circuit portion, said second thin film transistors constituting at least an X-decoder/driver, a Y-decoder/driver, a memory circuit and a CPU circuit, wherein a concentration of carbon, nitrogen or oxygen contained in an active semiconductor layer of said first thin film transistors is higher than a concentration of carbon, nitrogen or oxygen contained in an active semiconductor layer of said second thin film transistors.

Claim 24

A thin film semiconductor integrated circuit comprising: a substrate having an insulating surface, said substrate having an active matrix circuit portion and a peripheral circuit portion; a plurality of electrodes formed in the active matrix circuit portion; a plurality of first thin film transistors connected to said electrodes in the active matrix circuit portion; a plurality of second thin film transistors formed in said peripheral circuit portion, said second thin film transistors constituting at least an X-decoder/driver, a Y-decoder/driver, a memory circuit and a CPU circuit, wherein a concentration of carbon, nitrogen or oxygen contained in an active semiconductor layer of said first thin film transistors is higher than a concentration of carbon, nitrogen or oxygen contained in an active semiconductor layer of said second thin film transistors.

Claim 25

The integrated circuit of claim 21 wherein the concentration of carbon, nitrogen or oxygen in the active semiconductor layer of said first thin film transistor is not lower than 5×10 19 atoms/cm 3 .

Claim 26

The integrated circuit of claim 22 wherein the concentration of carbon, nitrogen or oxygen in the active semiconductor layer of said second thin film transistor is not higher than 1 ×10 19 atoms/cm 3 .

Claim 27

The integrated circuit of claim 21 further comprising a correction memory formed in said peripheral circuit portion and connected to said CPU circuit, wherein said correction memory is constituted by TFTs formed on said substrate.

Claim 28

The integrated circuit of claim 21 wherein each of said first thin film transistors is provided with a metal silicide layer within or in contact with source and drain regions thereof.

Claim 29

A semiconductor device comprising: a substrate having an insulating surface; a semiconductor layer formed on said insulating surface, said semiconductor layer comprising a first region, at least one second region and a pair of third regions, said first region functioning as a channel and said pair of third regions functioning as source and drain regions; a gate insulating layer located adjacent to said semiconductor layer; and a gate electrode located adjacent to said gate insulating layer, wherein said first and second regions extend between said pair of third regions and said at least one second region extends between said first region and at least one of said third regions, and wherein a total concentration of oxygen, carbon and nitrogen in said pair of third regions is higher than a total concentration of oxygen, carbon and nitrogen in said at least one second region.

Claim 30

A semiconductor device comprising: a substrate having an insulating surface; a semiconductor layer formed on said insulating surface, said semiconductor layer comprising a first region, at least one second region and a pair of third regions, said first region functioning as a channel and said pair of third regions functioning as source and drain regions; a gate insulating layer located adjacent to said semiconductor layer; and a gate electrode located adjacent to said gate insulating layer, wherein said first and second regions extend between said pair of third regions and said at least one second region extends between said first region and at least one of said third regions, and wherein a total concentration of oxygen, carbon and nitrogen in said pair of third regions is higher than a total concentration of oxygen, carbon and nitrogen in said at least one second region.

Claim 31

A semiconductor device comprising: a substrate having an insulating surface; a semiconductor layer formed on said insulating surface, said semiconductor layer comprising a first region, at least one second region and a pair of third regions, said first region functioning as a channel and said pair of third regions functioning as source and drain regions; a gate insulating layer located adjacent to said semiconductor layer; and a gate electrode located adjacent to said gate insulating layer, wherein said first and second regions extend between said pair of third regions and said at least one second region extends between said first region and at least one of said third regions, wherein a total concentration of oxygen, carbon and nitrogen in said at least one second region is higher than a total concentration of oxygen, carbon and nitrogen in said first region, and wherein a total concentration of oxygen, carbon and nitrogen in said pair of third regions is higher than a total concentration of oxygen, carbon and nitrogen in said second at least one region.

Claim 32

A semiconductor device comprising: a substrate having an insulating surface; a semiconductor layer formed on said insulating surface, said semiconductor layer comprising a first region, at least one second region and a pair of third regions, said first region functioning as a channel and said pair of third regions functioning as source and drain regions; a gate insulating layer located adjacent to said semiconductor layer; and a gate electrode located adjacent to said gate insulating layer, wherein said first and second regions extend between said pair of third regions and said at least one second region extends between said first region and at least one of said third regions, wherein a total concentration of oxygen, carbon and nitrogen in said at least one second region is higher than a total concentration of oxygen, carbon and nitrogen in said first region, and wherein a total concentration of oxygen, carbon and nitrogen in said pair of third regions is higher than a total concentration of oxygen, carbon and nitrogen in said second at least one region.

Claim 33

A semiconductor device comprising: a substrate having an insulating surface; a semiconductor layer formed on said insulating surface, said semiconductor layer comprising a first region, at least one second region and a pair of third regions, said first region functioning as a channel and said pair of third regions functioning as source and drain regions; a gate insulating layer located adjacent to said semiconductor layer; and a gate electrode located adjacent to said gate insulating layer, wherein said first and second regions extend between said pair of third regions and said at least one second region extends between said first region and at least one of said third regions, and wherein a band gap of said at least one second region is higher than a band gap of said first region.

Claim 34

A semiconductor device comprising: a substrate having an insulating surface; a semiconductor layer formed on said insulating surface, said semiconductor layer comprising a first region, at least one second region and a pair of third regions, said first region functioning as a channel and said pair of third regions functioning as source and drain regions; a gate insulating layer located adjacent to said semiconductor layer; and a gate electrode located adjacent to said gate insulating layer, wherein said first and second regions extend between said pair of third regions and said at least one second region extends between said first region and at least one of said third regions, and wherein a band gap of said at least one second region is higher than a band gap of said first region.

Claim 35

A semiconductor device comprising: a substrate having an insulating surface; a semiconductor layer formed on said insulating surface, said semiconductor layer comprising a first region, at least one second region and a pair of third regions, said first region functioning as a channel and said pair of third regions functioning as source and drain regions; a gate insulating layer located adjacent to said semiconductor layer; and a gate electrode located adjacent to said gate insulating layer, wherein said first and second regions extend between said pair of third regions and said at least one second region extends between said first region and at least one of third regions, and wherein band gaps of said pair of third regions are higher than a band gap of said at least one second region.

Claim 36

A semiconductor device comprising: a substrate having an insulating surface; a semiconductor layer formed on said insulating surface, said semiconductor layer comprising a first region, at least one second region and a pair of third regions, said first region functioning as a channel and said pair of third regions functioning as source and drain regions; a gate insulating layer located adjacent to said semiconductor layer; and a gate electrode located adjacent to said gate insulating layer, wherein said first and second regions extend between said pair of third regions and said at least one second region extends between said first region and at least one of third regions, and wherein band gaps of said pair of third regions are higher than a band gap of said at least one second region.

Claim 37

A semiconductor device comprising: a substrate having an insulating surface; a semiconductor layer formed on said insulating surface, said semiconductor layer comprising a first region, at least one second region and a pair of third regions, said first region functioning as a channel and said pair of third regions functioning as source and drain regions; a gate insulating layer located adjacent to said semiconductor layer; and a gate electrode located adjacent to said gate insulating layer, wherein said first and second regions extend between said pair of third regions and said at least one second region extends between said first region and at least one of said third regions, wherein a band gap of said at least one second region is higher than a band gap of said first region, and wherein band gaps of said pair of third regions are higher than a band gap of said at least one second region.

Claim 38

A semiconductor device comprising: a substrate having an insulating surface; a semiconductor layer formed on said insulating surface, said semiconductor layer comprising a first region, at least one second region and a pair of third regions, said first region functioning as a channel and said pair of third regions functioning as source and drain regions; a gate insulating layer located adjacent to said semiconductor layer; and a gate electrode located adjacent to said gate insulating layer, wherein said first and second regions extend between said pair of third regions and said at least one second region extends between said first region and at least one of said third regions, wherein a band gap of said at least one second region is higher than a band gap of said first region, and wherein band gaps of said pair of third regions are higher than a band gap of said at least one second region.