Semiconductor device for minimizing diffusion of conductivity enhancing impurities from one region of a polysilicon layer to another

Claim 2

A back-to-back diode resistor comprising: a polysilicon layer having two n-type regions separated by a p-type region, the polysilicon layer having interfaces between the p-type region and each of the n-type regions; and a diffusion barrier region disposed at each of the interfaces between the p-type region and the two n-type regions, the diffusion barrier regions having a selected width and containing a diffusion inhibiting impurity at a selected concentration, the p-type region being substantially void of the diffusion inhibiting impurity.

Claim 3

A back-to-back diode resistor according to claim 1 wherein the diffusion inhibiting impurity is selected from the group consisting of nitrogen, oxygen, and germanium.

Claim 4

A back-to-back diode resistor according to claim 1 wherein each of the diffusion barrier regions has a width of approximately 500 to approximately 3000 Angstroms.

Claim 5

A back-to-back diode resistor according to claim 1 wherein the diffusion inhibiting impurity is selected from the group consisting of nitrogen, oxygen, and germanium; and each of the diffusion barrier regions has a width of approximately 500 to approximately 3000 Angstroms.

Claim 6

A back-to-back diode resistor according to claim 1 wherein the diffusion inhibiting impurity is selected from the group consisting of nitrogen, oxygen, and germanium; and each of the diffusion barrier regions has a width of approximately 1000 Angstroms.

Claim 7

A back-to-back diode resistor according to claim 1 whereby the back-to-back diode resistor is approximately 2 microns or less in length.

Claim 8

An SRAM incorporating the back-to-back diode resistor of claim 1.

Claim 9

A semiconductor device comprising a polysilicon layer having first, second, and third regions, the second region being disposed between the first and third regions, the semiconductor device further comprising diffusion barrier regions of a predetermined width between the first and second regions and between the second and third regions, the second region being provided with a first impurity of a first conductivity type to a first concentration, the diffusion barrier regions being provided with a second impurity to a second concentration, and the first and third regions being provided with a third impurity of a second conductivity type opposite the first conductivity type, the first and third regions being provided to a third concentration greater than the first concentration.

Claim 10

A semiconductor device comprising a polysilicon layer having first, second, and third regions, the second region being disposed between the first and third regions, the semiconductor device further comprising diffusion barrier regions of a predetermined width between the first and second regions and between the second and third regions, the second region being provided with a first impurity of a first conductivity type to a first concentration, the diffusion barrier regions being provided with a second impurity to a second concentration, and the first and third regions being provided with a third impurity of a second conductivity type opposite the first conductivity type, the first and third regions being provided to a third concentration greater than the first concentration.

Claim 11

An SRAM memory device comprising: a first transistor having a source coupled to ground, a drain and a gate; a second transistor having a source coupled to ground, a drain coupled to the gate of the first transistor, and a gate coupled to the drain of the first transistor; a third transistor having a source coupled to a first bit line, a drain connected to the drain of the first transistor, and a gate connected to a word line; a fourth transistor having a source coupled to a second bit line, a drain connected to the drain of the second transistor, and a gate connected to the word line; a first resistive element coupled between the drain of the first transistor and a power source; and a second resistive element coupled between the drain of the second transistor and the power source; the first and second resistive elements being formed in a polysilicon layer, the polysilicon layer comprising: two n-type regions separated by a p-type region, the polysilicon layer having interfaces between the p-type region and each of the n-type regions; and a diffusion barrier region disposed at each of the interfaces between the p-type region and the two n-type regions, the diffusion barrier regions having a selected width and containing a diffusion inhibiting at a selected concentration, the p-type region being substantially void of the diffusion inhibiting impurity.

Claim 12

An SRAM memory device comprising: a first transistor having a source coupled to ground, a drain and a gate; a second transistor having a source coupled to ground, a drain coupled to the gate of the first transistor, and a gate coupled to the drain of the first transistor; a third transistor having a source coupled to a first bit line, a drain connected to the drain of the first transistor, and a gate connected to a word line; a fourth transistor having a source coupled to a second bit line, a drain connected to the drain of the second transistor, and a gate connected to the word line; a first resistive element coupled between the drain of the first transistor and a power source; and a second resistive element coupled between the drain of the second transistor and the power source; the first and second resistive elements being formed in a polysilicon layer, the polysilicon layer comprising: two n-type regions separated by a p-type region, the polysilicon layer having interfaces between the p-type region and each of the n-type regions; and a diffusion barrier region disposed at each of the interfaces between the p-type region and the two n-type regions, the diffusion barrier regions having a selected width and containing a diffusion inhibiting at a selected concentration, the p-type region being substantially void of the diffusion inhibiting impurity.