Method of fabricating a buried contact structure for SRAM

Claim 1

A method of fabricating a buried contact structure in a silicon substrate doped with impurities of a first conductivity type and having an active region isolated by a field oxide layer, comprising the steps of: (a) forming a gate oxide layer over said substrate; (b) forming a polysilicon layer over said gate oxide layer and said field oxide layer; (c) patterning and etching said polysilicon layer to form a gate electrode on said active region, an interconnect layer covering said field oxide layer, and an opening located between said gate electrode and said interconnect layer; (d) forming an oxide layer covering said interconnect layer and sidewalls of said interconnect layer said gate electrode and sidewalls of said gate electrode and said opening; (e) implanting impurities of a second conductivity type through said opening into said substrate to form a lightly-doped region beneath said opening; (f) forming a first spacer on said oxide layer on the sidewall of said interconnect layer and a second spacer on said oxide layer on the sidewall of said gate electrode; (g) removing said first spacer together with the underlying oxide layer to define a contact region adjacent to the sidewall of said interconnect layer and removing said oxide layer formed on the sidewall of said interconnect layer; (h) implanting impurities of the second conductivity type through said opening into said substrate to form a heavily-doped region between said lightly-doped region and said field oxide layer including a portion beneath said contact region; and (i) forming a silicide layer on said sidewall of said interconnect layer and said contact region to make electrical contact between the interconnect layer and said heavily-doped region through said contact region.

Claim 2

A method of fabricating a buried contact structure in a silicon substrate doped with impurities of a first conductivity type and having an active region isolated by a field oxide layer, comprising the steps of: (a) forming a gate oxide layer over said substrate; (b) forming a polysilicon layer over said gate oxide layer and said field oxide layer; (c) patterning and etching said polysilicon layer to form a gate electrode on said active region, an interconnect layer covering said field oxide layer, and an opening located between said gate electrode and said interconnect layer; (d) forming an oxide layer covering said interconnect layer and sidewalls of said interconnect layer said gate electrode and sidewalls of said gate electrode and said opening; (e) implanting impurities of a second conductivity type through said opening into said substrate to form a lightly-doped region beneath said opening; (f) forming a first spacer on said oxide layer on the sidewall of said interconnect layer and a second spacer on said oxide layer on the sidewall of said gate electrode; (g) removing said first spacer together with the underlying oxide layer to define a contact region adjacent to the sidewall of said interconnect layer and removing said oxide layer formed on the sidewall of said interconnect layer; (h) implanting impurities of the second conductivity type through said opening into said substrate to form a heavily-doped region between said lightly-doped region and said field oxide layer including a portion beneath said contact region; and (i) forming a silicide layer on said sidewall of said interconnect layer and said contact region to make electrical contact between the interconnect layer and said heavily-doped region through said contact region.