Method for making direct contacts in high density MOS/CMOS processes

Claim 1

A method for forming a direct contact between a conducting gate layer and a semiconductor device terminal region of a semiconducting substrate in a portion of an active area bounded by a dielectric field isolation layer, comprising the steps of: forming a dielectric gate isolation layer over said active area of said semiconducting substrate; defining a direct contact area by masking a defined area, said defined area having dimensions which are essentially smaller than those of said conducting gate layer; etching said dielectric gate isolation layer to expose said semiconducting substrate in said defined area; and implanting an implant zone geometrically overlapping at least a portion of said direct contact area and at least a portion of said terminal region, so as to produce a connecting diffusion in said semiconducting substrate forming said active area including said direct contact, said direct contact providing electrical continuity between said conducting gate layer and said terminal region.

Claim 2

A method for forming a direct contact between a conducting gate layer and a semiconductor device terminal region of a semiconducting substrate in a portion of an active area bounded by a dielectric field isolation layer, comprising the steps of: forming a dielectric gate isolation layer over said active area of said semiconducting substrate; defining a direct contact area by masking a defined area, said defined area having dimensions which are essentially smaller than those of said conducting gate layer; etching said dielectric gate isolation layer to expose said semiconducting substrate in said defined area; and implanting an implant zone geometrically overlapping at least a portion of said direct contact area and at least a portion of said terminal region, so as to produce a connecting diffusion in said semiconducting substrate forming said active area including said direct contact, said direct contact providing electrical continuity between said conducting gate layer and said terminal region.

Claim 7

A method for forming a direct contact between a conducting gate layer and a semiconductor device terminal region of a semiconducting substrate, said direct contact including a portion of an active area of said semiconducting substrate bounded by a dielectric field isolation layer, comprising the steps of: defining an implant zone by masking a portion of said active area; implanting and diffusing said implant zone with a dopant; forming a dielectric gate isolation layer over said active area; depositing a first conducting layer over said gate isolation layer and over said field isolation layer; defining at least one edge of a direct contact area by masking a portion of said implant zone; etching said first conducting layer and said gate isolation layer to expose said semiconducting substrate corresponding to said direct contact area; depositing a second conducting layer over said substrate inside said direct contact area and over said first conducting layer outside said direct contact area; forming a mask for patterning said conducting gate layer having a patterning profile around said direct contact area with dimensions that are essentially larger than dimensions of definition of said direct contact area and essentially smaller than dimensions of definition of said implant zone; and removing said dielectric gate layer from areas not covered by said conducting gate layer; implanting and diffusing a dopant for forming a terminal region of a semiconductor device aligned with at least a definition edge of said conducting gate layer, said terminal region overlapping said direct contact area.

Claim 8

A method for forming a direct contact between a conducting gate layer and a semiconductor device terminal region of a semiconducting substrate, said direct contact including a portion of an active area of said semiconducting substrate bounded by a dielectric field isolation layer, comprising the steps of: defining an implant zone by masking a portion of said active area; implanting and diffusing said implant zone with a dopant; forming a dielectric gate isolation layer over said active area; depositing a first conducting layer over said gate isolation layer and over said field isolation layer; defining at least one edge of a direct contact area by masking a portion of said implant zone; etching said first conducting layer and said gate isolation layer to expose said semiconducting substrate corresponding to said direct contact area; depositing a second conducting layer over said substrate inside said direct contact area and over said first conducting layer outside said direct contact area; forming a mask for patterning said conducting gate layer having a patterning profile around said direct contact area with dimensions that are essentially larger than dimensions of definition of said direct contact area and essentially smaller than dimensions of definition of said implant zone; and removing said dielectric gate layer from areas not covered by said conducting gate layer; implanting and diffusing a dopant for forming a terminal region of a semiconductor device aligned with at least a definition edge of said conducting gate layer, said terminal region overlapping said direct contact area.

Claim 11

A method for forming a direct contact between a conducting gate layer and a semiconductor device terminal region of a semiconducting substrate, said direct contact including a portion of an active area of said semiconducting substrate bounded by a dielectric field isolation layer, comprising the steps of: defining an implant zone by masking a portion of said active area; implanting and diffusing said implant zone with a dopant; forming a dielectric gate isolation layer over said active area; depositing a first conducting layer over said gate isolation layer and over said field isolation layer; defining at least one edge of a direct contact area by masking a portion of said implant zone; etching said first conducting layer and said gate isolation layer to expose said semiconducting substrate corresponding to said direct contact area; depositing a second conducting layer over said substrate inside said direct contact area and over said first conducting layer outside said direct contact area; forming said conducting gate layer over and wholly covering said direct contact area, and wholly covered by said second layer; removing said dielectric gate layer from areas not covered by said conducting gate layer; and implanting and diffusing a dopant for forming a terminal region of a semiconductor device aligned with at least a definition edge of said conducting gate layer, said terminal region overlapping said direct contact.

Claim 12

A method for forming a direct contact between a conducting gate layer and a semiconductor device terminal region of a semiconducting substrate, said direct contact including a portion of an active area of said semiconducting substrate bounded by a dielectric field isolation layer, comprising the steps of: defining an implant zone by masking a portion of said active area; implanting and diffusing said implant zone with a dopant; forming a dielectric gate isolation layer over said active area; depositing a first conducting layer over said gate isolation layer and over said field isolation layer; defining at least one edge of a direct contact area by masking a portion of said implant zone; etching said first conducting layer and said gate isolation layer to expose said semiconducting substrate corresponding to said direct contact area; depositing a second conducting layer over said substrate inside said direct contact area and over said first conducting layer outside said direct contact area; forming said conducting gate layer over and wholly covering said direct contact area, and wholly covered by said second layer; removing said dielectric gate layer from areas not covered by said conducting gate layer; and implanting and diffusing a dopant for forming a terminal region of a semiconductor device aligned with at least a definition edge of said conducting gate layer, said terminal region overlapping said direct contact.