US4994894A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor device having an improved wiring pattern
Assignee: Toshiba Corp
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Filing: 1989-01-05
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Granted: 1991-02-19
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Expires: 2009-01-05
Abstract
Abstract A semiconductor device comprises a semiconductor substrate having a diffused region and an element region, and the diffused region and the element region overlap at least partially. An insulating layer having a contact hole is provided at the surface of the substrate. A wiring layer crosses over the contact hole to form at least four crossing points with respect to the contact hole. The crossing points over the element region correspond to the overlap between the diffused region and the element region.
Inventors
- 👤 Takeo Nakayama
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 19:31
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/40
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
127 words
In a semiconductor device comprising, a semiconductor substrate of a first conductivity type, an insulating layer formed on the substrate, an opening in the insulating layer exposing a portion of the substrate, a wiring layer containing impurities of a second conductivity type, a diffused region in the exposed portion of the substrate containing diffused impurities from the wiring layer, and an element region of the second conductivity type containing implanted impurities of the second conductivity type; the improvement comprising, the opening being in the shape of a pentagon and the wiring layer crossing a perimeter of the opening at least least four locations of direct contact between the wiring layer and the diffused region to connect the wiring layer with the element region through the diffused region.
Claim 2
Dependent Claim
127 words
In a semiconductor device comprising, a semiconductor substrate of a first conductivity type, an insulating layer formed on the substrate, an opening in the insulating layer exposing a portion of the substrate, a wiring layer containing impurities of a second conductivity type, a diffused region in the exposed portion of the substrate containing diffused impurities from the wiring layer, and an element region of the second conductivity type containing implanted impurities of the second conductivity type; the improvement comprising, the opening being in the shape of a pentagon and the wiring layer crossing a perimeter of the opening at least least four locations of direct contact between the wiring layer and the diffused region to connect the wiring layer with the element region through the diffused region.
References Cited (Backward Citations)
US4549199A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-02-18 | 1994-08-20 | 1995-02-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-02-18 | 1998-08-20 | 1999-02-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-02-18 | 2002-08-20 | 2003-02-19 | $7700.00 | Window Closed / Lapsed |