Clock change circuit preventing spike generation by delaying selection control signal

Claim 1

A clock change circuit comprising: clock gate means for receiving first and second clock signals, and outputting an active timing signal when both said first and second clock signals are at an inactive level, said active timing signal indicating the timing; delay means being input a select control signal and the active timing signal, and for outputting a delayed select control signal the state of which is changed to the same state as the select control signal after the active timing signal is received from the clock gate means; select means being input the first and second clock signals, and for selecting one of the first and second clock signals according to the delayed select control signal to output the selected clock signal; fixed receiving clock generation means for generating a fixed receiving clock signal having a predetermined frequency and a predetermined phase; original receiving clock detect means for being input a data signal, and detecting timing information included in the data signal to generate an original receiving clock signal in synchronization with the data signal, based on the timing information; adaptive clock generation means for inputting the original receiving clock signal, outputting an adaptive clock signal, detecting a phase difference between the adaptive clock signal and the original receiving clock signal, and shifting the, phase of the adaptive clock signal so that the phase difference becomes equal to a predetermined value; and clock change signal generation means for determining whether or not the phase of the original receiving clock signal is within a predetermined range from the phase of a transmission frame synchronization clock, and outputting as the select control signal a signal the state of which varies dependent upon whether or not the phase of the original receiving clock signal is within the predetermined range from the phase of the transmission frame synchronization clock.