Circuit having a master-and-slave and a by-pass

Claim 1

A semiconductor integrated circuit including a sequential circuit capable of operating synchronously with a clock signal comprising: a first storage circuit having a write state and hold state where input data supplied from a main data input terminal can be written and held is controlled in accordance with first and second control signals; a second storage circuit coupled between said first storage circuit and a data output terminal, having a write state and hold state in which output data from the first storage circuit can be written and held are controlled in accordance with a third control signal; and a bypass circuit connected to the main data input terminal and the data output terminal, in which data transfer time until the input data supplied from the main data input terminal reaches the data output terminal is shorter than time taken for the input data to pass through both the storage circuits, an output operation of the bypass circuit is inhibited according to states of the second and third control signals when the second and third control signals master/slave operate the first and second storage circuits, and the output operation of the bypass circuit to transfer data to the data output terminal is enabled according to the state of the third control signal when the second storage circuit is instructed to operate in a normal write state and according to the states of the first and second control signals for controlling the state where the input data sent from the main data input terminal is written in the first storage circuit; wherein the sequential circuit comprises the first storage circuit, second storage circuit, and bypass circuit.