Patent US5579326A successfully refreshed from Google Patents.
US5579326A
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Method and apparatus for programming signal timing
Assignee: STMicroelectronics lnc USA
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Filing: 1994-01-31
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Granted: 1996-11-26
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Expires: 2014-01-31
Abstract
Abstract A method and apparatus for testing and programming signal timing are disclosed which can be incorporated into an integrated circuit device utilizing on-chip timed command signals and pulses. The method of the invention enables nonpermanent testing and retesting of a device at various operational speeds during production testing. During retesting, temporary signal delays are selectively introduced into the circuit of a device which failed a previous test due to non-repairable errors. Once a device passes the production test error-free or with repairable errors, the temporary signal delays are permanently programmed into the device. Specifically, the method utilizes one or a plurality of mode control circuits and test voltage input terminals to nonpermanently select signal delays which may be identified and permanently enabled at a later time.
Inventors
- 👤 David C. McClure
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 12:57
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/02; G11C29/026; G01; G01R; G01R31/00; G01R31/28; G01R31/30; G06; G06F; G06F11/00; G06F11/006; G11C29/028; G11C29/04; G11C29/08; G11C29/12; G11C29/44; G11C29/50; G11C29/50012; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/41
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
125 words
A method of testing a device, comprising the steps of: transmitting a signal to a mode control circuit, wherein said mode control circuit generates an output signal to a programmable delay circuit; testing said device for a first operational speed; analyzing the test results for said first operational speed; testing said device for a second operational speed if said analyzing step for said first operational speed indicates an alternate operational speed is desired, said second operational speed having a first delay mode enabled by said mode control circuit; analyzing the test results for said second operational speed; and permanently programming said device for the first delay mode if said analyzing step for said second operational speed indicates a third alternate operational speed is not desired.
Claim 2
Independent Claim
125 words
A method of testing a device, comprising the steps of: transmitting a signal to a mode control circuit, wherein said mode control circuit generates an output signal to a programmable delay circuit; testing said device for a first operational speed; analyzing the test results for said first operational speed; testing said device for a second operational speed if said analyzing step for said first operational speed indicates an alternate operational speed is desired, said second operational speed having a first delay mode enabled by said mode control circuit; analyzing the test results for said second operational speed; and permanently programming said device for the first delay mode if said analyzing step for said second operational speed indicates a third alternate operational speed is not desired.
Claim 3
Dependent Claim
87 words
The method of claim 1, further comprising the steps of: testing said device for a third operational speed if said analyzing step for said second operational speed indicates a third alternate operational speed is desired, said third operational speed having a second delay mode nonpermanently enabled by said mode control circuit; analyzing test results for said third operational speed; and permanently programming said device for the second delay mode if said analyzing step for said third operational speed indicates a subsequent alternate operational speed is not desired.
Claim 4
Dependent Claim
15 words
The method of claim 1, wherein said programmable delay circuit comprises variable impedance delay elements.
Claim 5
Dependent Claim
15 words
The method of claim 1, wherein said programmable delay circuit controls a sense amplifier circuit.
Claim 6
Dependent Claim
16 words
The method of claim 1, wherein said programmable delay circuit controls an edge transition detection circuit.
Claim 7
Dependent Claim
17 words
The method of claim 1, wherein said first operational speed is slower than said second operational speed.
Claim 8
Dependent Claim
17 words
The method of claim 1, wherein said first operational speed is faster than said second operational speed.
Claim 9
Dependent Claim
41 words
The method of claim 7, wherein said analyzing step for said first operational speed identified non-repairable errors during operation of the device, and said analyzing step for said second operational speed did not identify non-repairable errors during operation of the device.
Claim 10
Dependent Claim
31 words
The method of claim 1, wherein the step of transmitting a signal to the mode control circuit comprises applying a test voltage to a test voltage input terminal of the device.
Claim 11
Dependent Claim
24 words
The method of claim 1, wherein the step of programming said device for the first delay mode comprises the step of blowing a fuse.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-11-26 | 2000-05-27 | 2000-11-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-11-26 | 2004-05-27 | 2004-11-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-11-26 | 2008-05-27 | 2008-11-26 | $7700.00 | Window Closed / Lapsed |