US5384741A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor memory device adapted for preventing a test mode operation from undesirably occurring
Assignee: Mitsubishi Electric Corp
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Filing: 1994-01-27
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Granted: 1995-01-24
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Expires: 2014-01-27
Abstract
Abstract A semiconductor memory device having a circuit for preventing the operation of a test mode includes a first terminal for receiving an externally applied high voltage exceeding a power supply potential, a second terminal for receiving an externally applied test mode signal and a high voltage detector for detecting that a high voltage signal has been applied through the first terminal. A test mode signal holding circuit is responsive to the high voltage detector and holds the test mode signal applied through the second terminal. A test circuit is responsive to the test mode signal held in the test mode signal holding circuit and performs a test in the semiconductor memory device. A disabling circuit is provided to disable the high voltage detector.
Inventors
- 👤 Yoshiyuki Haraguchi
- 👤 Yutaka Arita
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 08:21
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/04; G11C29/08; G11C29/12; G11C29/46
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
127 words
A semiconductor memory device, comprising: a first terminal for receiving a high voltage which is externally applied and exceeds a power supply potential; a second terminal for receiving an externally applied test mode signal; high voltage detecting means for detecting that a high voltage signal has been applied through said first terminal; test mode signal holding means responsive to said high voltage detecting means for holding the test mode signal applied through said second terminal; test circuit means responsive to the test mode signal held in said test mode signal holding means for performing a test in said semiconductor memory device; disabling means for disabling a detecting operation by said high voltage detecting means when the test should not be carried out by said test circuit means.
Claim 2
Dependent Claim
127 words
A semiconductor memory device, comprising: a first terminal for receiving a high voltage which is externally applied and exceeds a power supply potential; a second terminal for receiving an externally applied test mode signal; high voltage detecting means for detecting that a high voltage signal has been applied through said first terminal; test mode signal holding means responsive to said high voltage detecting means for holding the test mode signal applied through said second terminal; test circuit means responsive to the test mode signal held in said test mode signal holding means for performing a test in said semiconductor memory device; disabling means for disabling a detecting operation by said high voltage detecting means when the test should not be carried out by said test circuit means.
Claim 3
Dependent Claim
40 words
The semiconductor memory device according to claim 1, wherein said disabling means comprises disconnecting circuit means for disconnecting said high voltage detecting means from said first terminal when the test should not be carried out by said test circuit means.
Claim 4
Dependent Claim
55 words
The semiconductor memory device according to claim 2, wherein said disconnecting circuit means comprises fuse means connected between said first terminal and said high voltage detecting means, and current path means for forming a current path for fusing said fuse means so that the test may not be carried out by said test circuit means.
Claim 5
Dependent Claim
56 words
The semiconductor memory device according to claim 1, wherein said high voltage detecting means comprises voltage reducing means for reducing a voltage of the high voltage signal applied through said first terminal, and level comparing means for comparing the level of the voltage signal provided from said voltage reducing means with a predetermined threshold voltage level.
Claim 6
Dependent Claim
45 words
The semiconductor memory device according to claim 2, wherein said high voltage detecting means provides a disabling signal for disabling a holding operation by said test mode signal holding means when said disconnecting circuit means disconnects said high voltage detecting means from said first terminal.
Claim 7
Dependent Claim
45 words
The semiconductor memory device according to claim 1, wherein said test mode signal holding means comprises latch circuit means for latching a test mode signal applied through said second terminal, and means responsive to said high voltage detecting means for enabling said latch circuit means.
Claim 8
Dependent Claim
40 words
The semiconductor memory device according to claim 6, wherein said test mode signal holding means further comprises means responsive to the test mode signal applied through said second terminal for changing the signal latch state of said latch circuit means.
Claim 9
Dependent Claim
41 words
The semiconductor memory device according to claim 1, wherein said test mode signal holding means automatically generates and holds a non-test mode signal for preventing the test mode operation from occurring when the supply of a power supply voltage is started.
Claim 10
Dependent Claim
68 words
The semiconductor memory device according to claim 1, further comprising a plurality of memory cell arrays each provided with a plurality of memory cells arranged in rows and columns, wherein said test circuit means comprises match detecting means responsive to the test mode signal held in said test mode signal holding means for detecting a match of data signals read out from said plurality of memory cell arrays.
Claim 11
Dependent Claim
35 words
The semiconductor memory device according to claim 1, wherein at least one of said first and second terminals is shared to receive an externally applied control signal for controlling the operation in said memory device.
Claim 12
Dependent Claim
18 words
The semiconductor memory device according to claim 1, wherein said memory device is a static random access memory.
Claim 13
Dependent Claim
86 words
A semiconductor memory device, comprising: a predetermined terminal for receiving an externally applied voltage signal; high voltage detecting means for detecting that a voltage signal higher in magnitude than a power supply voltage has been applied through said predetermined terminal; test circuit means responsive to said high voltage detecting means for performing a test in said semiconductor memory device; disconnecting circuit means for disconnecting said high voltage detecting means from said predetermined terminal when the test should not be carried out by said test circuit means.
Claim 14
Dependent Claim
86 words
A semiconductor memory device, comprising: a predetermined terminal for receiving an externally applied voltage signal; high voltage detecting means for detecting that a voltage signal higher in magnitude than a power supply voltage has been applied through said predetermined terminal; test circuit means responsive to said high voltage detecting means for performing a test in said semiconductor memory device; disconnecting circuit means for disconnecting said high voltage detecting means from said predetermined terminal when the test should not be carried out by said test circuit means.
References Cited (Backward Citations)
US5155701A
Cited
US4841233A
Cited
US4956816A
Cited
US4896055A
Cited
US5023840A
Cited
US5132937A
Cited
EP0407173A2
Cited
US5233610A
Cited
US5155704A
Cited
US5208777A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-01-23 | 1998-07-25 | 1999-01-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-01-23 | 2002-07-25 | 2003-01-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-01-23 | 2006-07-25 | 2007-01-24 | $7700.00 | Window Closed / Lapsed |