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US5208777A
Expired / Lapsed
US
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Semiconductor memory device
Assignee: NEC Corp
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Filing: 1991-12-02
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Granted: 1993-05-04
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Expires: 2011-12-02
Abstract
Abstract A circuit for carrying out ordinary "write" and "read" operation during operation of applying a test voltage to a cell opposite electrode in test operation is provided. The circuit converts a test mode instruction signal to an ordinary operation instruction signal in a semiconductor memory device. The test mode instruction signal can be applied to an input pin of the semiconductor memory device, so that the test operation can be carried out even after the assembly of the semiconductor memory device.
Inventors
- 👤 Kazuo Shibata
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 05:10
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/04; G11C29/50; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
126 words
A semiconductor memory device, comprising: capacitive memory cells each having first and second electrodes for sandwiching a dielectric member therebetween, said first electrode accumulating a bit of stored information, and said second electrode being fixed by a predetermined voltage in ordinary "write" and "read" operation; a voltage applying circuit for applying a volt selected from a power supply voltage of "Vcc", an intermediate voltage of "1/2 Vcc" and a voltage of ground level to said second electrode in test operation by receiving a test mode instruction signal; and an operation carrying-out circuit for carrying out said ordinary "write" and "read" operation during said test operation, said operation carrying-out circuit converting said test mode instruction signal to an instruction signal of said ordinary "write" and "read" operation.
Claim 2
Dependent Claim
126 words
A semiconductor memory device, comprising: capacitive memory cells each having first and second electrodes for sandwiching a dielectric member therebetween, said first electrode accumulating a bit of stored information, and said second electrode being fixed by a predetermined voltage in ordinary "write" and "read" operation; a voltage applying circuit for applying a volt selected from a power supply voltage of "Vcc", an intermediate voltage of "1/2 Vcc" and a voltage of ground level to said second electrode in test operation by receiving a test mode instruction signal; and an operation carrying-out circuit for carrying out said ordinary "write" and "read" operation during said test operation, said operation carrying-out circuit converting said test mode instruction signal to an instruction signal of said ordinary "write" and "read" operation.
Claim 3
Dependent Claim
57 words
A semiconductor memory device, according to claim 1, wherein: said voltage applying circuit comprises a high voltage decision circuit for detecting a changing level of said test mode instruction signal, one of said power supply voltage of "Vcc", said intermediate voltage of "1/2 Vcc", and said voltage of ground level being selected dependent on said changing level.
Claim 4
Dependent Claim
65 words
A semiconductor memory device, according to claim 1, wherein: said test mode signal is of a voltage greater than said power supply voltage of "Vcc", and is applied to an input pin selected from external signal input pins of said semiconductor memory device, said external signal input pins being applied with one of said power supply voltage of "Vcc" and said voltage of ground level.
Claim 5
Dependent Claim
61 words
A semiconductor memory device, according to claim 1, further comprising: a CBR decision circuit for deciding whether CBR (CAS-Before-RAS) operation is carried out or not; and an output control circuit for controlling an output signal to be high or low dependent on a level of said test mode instruction signal by receiving a decision signal supplied from said CBR decision circuit.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-05-03 | 1996-11-02 | 1997-05-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-05-03 | 2000-11-02 | 2001-05-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-05-03 | 2004-11-02 | 2005-05-04 | $7700.00 | Window Closed / Lapsed |