US5361230A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Memory device delaying timing of outputting data in a test mode as compared with a normal operating mode
Assignee: Mitsubishi Electric Corp
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Filing: 1993-05-28
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Granted: 1994-11-01
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Expires: 2013-05-28
Abstract
Abstract The present invention relates to a memory device having reduced access time of memory cells in a test mode. The memory device forms, in the test mode, read data D R by applying Ex-OR processing to a plurality of data read from a memory cell array 11 by a data processing circuit 5, to provide the formed data to the outside through a data output circuit 6. The timing of the output of data to the outside is delayed, by delay circuit 12 in the test mode, than that in the normal operation by a time period corresponding to time required for the EX-OR processing in data processing circuit 5. Consequently, output of invalid data to the outside can be prevented, and thus access time of valid data can be reduced.
Inventors
- 👤 Yuto Ikeda
- 👤 Yoshinori Inoue
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 17:03
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/04; G11C29/08; G11C29/12; G11C29/14; G11C29/12015
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
110 words
A memory device operable in a test mode and a normal operation mode comprising: a plurality of memory cells; data reading means for reading data from respective ones of memory cells selected from said plurality of memory cells; data processing means for applying a predetermined logical operation processing to said data read from said selected memory cells to convert said read data into data the number of which is less than that of said read data in the test mode; and control means for delaying the timing of output of said data from said data processing means in the test mode as compared with that in the normal operation mode.
Claim 2
Dependent Claim
110 words
A memory device operable in a test mode and a normal operation mode comprising: a plurality of memory cells; data reading means for reading data from respective ones of memory cells selected from said plurality of memory cells; data processing means for applying a predetermined logical operation processing to said data read from said selected memory cells to convert said read data into data the number of which is less than that of said read data in the test mode; and control means for delaying the timing of output of said data from said data processing means in the test mode as compared with that in the normal operation mode.
Claim 3
Dependent Claim
36 words
The memory device according to claim 1, wherein said data processing means selects at least one data among said data read from said selected memory cells to provide the selected data in the normal operation mode.
Claim 4
Dependent Claim
93 words
The memory device according to claim 2, wherein said data processing means includes logical operation means for applying said predetermined logical operation processing to said data read from said selected memory cells, means for selecting at least one data from said data read from said selected memory cells, and switching means responsive to a mode designating signal applied externally, for selecting and providing an output of said selecting means when the normal operation mode is designated, and selecting and providing an output of said logical operation means when the test mode is designated.
Claim 5
Dependent Claim
17 words
The memory device according to claim 3, wherein said predetermined logical operation processing is exclusive OR processing.
Claim 6
Dependent Claim
32 words
The memory device according to claim 1, further comprising data output means responsive to an output of said control means output for defining timing of data output from said data processing means.
Claim 7
Dependent Claim
60 words
The memory device according to claim 5, wherein said control means includes output control means responsive to a timing signal externally applied for driving said data output means, and delay means for delaying said timing signal in the test mode as compared with that in the normal operation mode to apply the delayed timing signal to said data output means.
Claim 8
Dependent Claim
52 words
The memory device according to claim 6, wherein said delay means includes delay circuit means enabled only when the test mode is designated in response to a test mode signal externally applied, and AND means for applying AND operation to said externally applied timing signal and an output of said delay means.
Claim 9
Dependent Claim
202 words
A memory device having a test function, comprising: a memory cell array including a plurality of memory cells; data reading means for reading data from respective ones of memory cells selected from said memory cell array; means for applying a mode designating signal designating either a normal operation mode or a test mode; data processing means for selecting at least one data from said data read from said selected memory cells to provide the selected data when said mode designating signal indicates the normal operation mode, and for applying a predetermined logical operation processing to said data read from said selected memory cells with a certain delay time period to convert said read data into data the number of which is less than that of said read data to provide the converted data when said mode designating signal indicates the test mode; and control means for providing an output data from said data processing means at a predetermined timing when said mode designating signal indicates said normal operation mode, and providing an output data from said data processing means at a timing delayed by said certain delay time period from said predetermined timing when said mode designating signal indicates the test mode.
Claim 10
Dependent Claim
202 words
A memory device having a test function, comprising: a memory cell array including a plurality of memory cells; data reading means for reading data from respective ones of memory cells selected from said memory cell array; means for applying a mode designating signal designating either a normal operation mode or a test mode; data processing means for selecting at least one data from said data read from said selected memory cells to provide the selected data when said mode designating signal indicates the normal operation mode, and for applying a predetermined logical operation processing to said data read from said selected memory cells with a certain delay time period to convert said read data into data the number of which is less than that of said read data to provide the converted data when said mode designating signal indicates the test mode; and control means for providing an output data from said data processing means at a predetermined timing when said mode designating signal indicates said normal operation mode, and providing an output data from said data processing means at a timing delayed by said certain delay time period from said predetermined timing when said mode designating signal indicates the test mode.
References Cited (Backward Citations)
US4630239A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-10-31 | 1998-05-02 | 1998-11-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-10-31 | 2002-05-02 | 2002-11-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-10-31 | 2006-05-02 | 2006-11-01 | $7700.00 | Window Closed / Lapsed |