Integrated circuit data processor which provides external sensibility of internal signals during reset

Claim 2

A data processing system, comprising: bus interface means for communicating an address value, a data value, a control value and a reset signal; a system clock circuit for communicating a system clock signal; a simulation clock generator coupled to the system clock circuit for receiving the system clock signal, the simulation clock generator providing an internal conditioned clock signal in response to the system clock signal; mode control means for determining a mode of operation of the data processing system in response to the reset signal, the mode control means being coupled to the bus interface means for receiving reset signal, the mode control means providing a mode signal in a first logic state when the data processing system is operating in a first mode of operation and providing the mode signal in a second logic state when the data processing system is operating in a second mode of operation; and bus control means for providing a first information value when the data processing system is in the first mode of operation and for providing the internal conditioned clock signal when the data processing system is in the second mode of operation, the bus control means being coupled to the bus interface means for receiving the reset signal, being coupled to the mode control means for receiving the mode signal, and being coupled to the simulation clock generator for receiving the internal conditioned clock signal.

Claim 3

The data processing system of claim 1 wherein the internal conditioned clock signal is provided externally when the data processing system is in the second mode of operation and the reset signal is asserted.

Claim 4

The data processing system of claim 1 further comprising: a bus multiplexer for communicating an external address value, an external data value, an external control value, and an external reset signal, the bus multiplexer being coupled to the bus interface means for communicating an address value, a data value, a control value, and the reset signal, the bus multiplexer being coupled to the bus control means for receiving the first information value when the data processing system is in the first mode of operation and for providing the internal conditioned clock signal when the data processing system is in the second mode of operation and the reset signal is asserted.

Claim 5

The data processing system of claim 3 further comprising: a plurality of integrated circuit terminals coupled to the bus multiplexer for communicating the external address value, the external data value, the external control value, the reset signal, and the system clock signal, the plurality of integrated circuit terminals communicating the first information value when the data processing system is in the first mode of operation and communicating the internal conditioned clock signal when the data processing system is in the second mode of operation and the reset signal is asserted.

Claim 6

The data processing system of claim 1 wherein the first information value is the address information value.

Claim 7

The data processing system of claim 1 wherein the first mode of operation is a normal mode of operation and the second mode of operation is an emulation mode of operation.

Claim 8

The data processing system of claim 1 wherein the internal conditioned clock signal is provided by the bus control means when the data processing system is in the second mode of operation and when the reset signal is in a first logic state.

Claim 9

A development system, comprising: a data processor, comprising: bus interface means for communicating an address value, a data value, a control value and a reset signal; a system clock circuit for communicating a system clock signal; a simulation clock generator coupled to the system clock circuit for receiving the system clock signal, the simulation clock generator providing an internal conditioned clock signal in response to the system clock signal; mode control means for determining a mode of operation of the data processor in response to the reset signal, the mode control means being coupled to the bus interface means for receiving reset signal, the mode control means providing a mode signal in a first logic state when the data processor is operating in a first mode of operation and providing the mode signal in a second logic state when the data processor is operating in a second mode of operation; bus control means for providing a first information value when the data processor is in the first mode of operation and for providing the internal conditioned clock signal when the data processor is in the second mode of operation, the bus control means being coupled to the bus interface means for receiving the reset signal, being coupled to the mode control means for receiving the mode control signal, and being coupled to the simulation clock generator for receiving the internal conditioned clock signal; a plurality of integrated circuit terminals coupled to the bus control means for communicating an external address value, an external data value, an external control value, the reset signal, and the system clock signal, the plurality of integrated circuit terminals communicating the first information value when the data processor is in the first mode of operation and communicating the internal conditioned clock signal when the data processor is in the second mode of operation and the reset signal is asserted; and a control register for storing a divide rate value, the divide rate value indicating a relation between the system clock signal and the internal conditioned clock signal, the control register being coupled to the bus interface means for receiving the address value, the data value, the control value, and the reset signal; and an emulation system, comprising: a shadow control register for storing a copy of the control register, the shadow control register being coupled to a first portion of the plurality of integrated circuit terminals for receiving the external data value and the external control value, the shadow control register storing a shadow divide rate; a synchronization circuit coupled to a second portion of the plurality of integrated circuit terminals for receiving the reset signal and the system clock signal, the synchronization circuit providing a synchronization signal; an emulator function circuit coupled to the plurality of integrated circuit terminals for receiving the external data value, the external address value, the external control value, and the reset signal for providing a write indicator circuit to indicate the divide rate value stored in the control register has been modified; and a clock synthesis circuit coupled to the shadow control register for receiving the shadow divide rate, coupled to a second portion of the plurality of integrated circuit terminals for receiving the system clock signal, and coupled to the synchronization circuit for receiving the synchronization signal, the clock synthesis circuit providing an external conditioned clock signal which is substantially similar to the internal conditioned clock signal.

Claim 10

A development system, comprising: a data processor, comprising: bus interface means for communicating an address value, a data value, a control value and a reset signal; a system clock circuit for communicating a system clock signal; a simulation clock generator coupled to the system clock circuit for receiving the system clock signal, the simulation clock generator providing an internal conditioned clock signal in response to the system clock signal; mode control means for determining a mode of operation of the data processor in response to the reset signal, the mode control means being coupled to the bus interface means for receiving reset signal, the mode control means providing a mode signal in a first logic state when the data processor is operating in a first mode of operation and providing the mode signal in a second logic state when the data processor is operating in a second mode of operation; bus control means for providing a first information value when the data processor is in the first mode of operation and for providing the internal conditioned clock signal when the data processor is in the second mode of operation, the bus control means being coupled to the bus interface means for receiving the reset signal, being coupled to the mode control means for receiving the mode control signal, and being coupled to the simulation clock generator for receiving the internal conditioned clock signal; a plurality of integrated circuit terminals coupled to the bus control means for communicating an external address value, an external data value, an external control value, the reset signal, and the system clock signal, the plurality of integrated circuit terminals communicating the first information value when the data processor is in the first mode of operation and communicating the internal conditioned clock signal when the data processor is in the second mode of operation and the reset signal is asserted; and a control register for storing a divide rate value, the divide rate value indicating a relation between the system clock signal and the internal conditioned clock signal, the control register being coupled to the bus interface means for receiving the address value, the data value, the control value, and the reset signal; and an emulation system, comprising: a shadow control register for storing a copy of the control register, the shadow control register being coupled to a first portion of the plurality of integrated circuit terminals for receiving the external data value and the external control value, the shadow control register storing a shadow divide rate; a synchronization circuit coupled to a second portion of the plurality of integrated circuit terminals for receiving the reset signal and the system clock signal, the synchronization circuit providing a synchronization signal; an emulator function circuit coupled to the plurality of integrated circuit terminals for receiving the external data value, the external address value, the external control value, and the reset signal for providing a write indicator circuit to indicate the divide rate value stored in the control register has been modified; and a clock synthesis circuit coupled to the shadow control register for receiving the shadow divide rate, coupled to a second portion of the plurality of integrated circuit terminals for receiving the system clock signal, and coupled to the synchronization circuit for receiving the synchronization signal, the clock synthesis circuit providing an external conditioned clock signal which is substantially similar to the internal conditioned clock signal.

Claim 11

The data processor of claim 8 wherein one of the external data value, the external address value, and the external control value is replaced by the internal conditioned clock signal when the data processor is operating in the second mode of operation.

Claim 14

The method of claim 10 wherein the predetermined mode of operation is an emulation mode of operation.

Claim 15

The method of claim 10 further comprising the steps of: determining when an internal register of the data processing system is written to modify a parameter of the internal signal; and providing an indicator signal via an integrated circuit terminal.

Claim 18

The method of claim 13 wherein the internal conditioned clock signal is provided externally when the data processing system is in the second mode of operation and the reset signal is asserted.

Claim 19

The method of claim 13 further comprising the step of: communicating an external address value, an external data value, an external control value, and an external reset signal using a bus multiplexer, the bus multiplexer being coupled to the bus interface means for receiving the address value, the data value, the control value, and the reset signal, the bus multiplexer being coupled to the bus control means for receiving the first information value when the data processing system is in the first mode of operation and for providing the internal conditioned clock signal when the data processing system is in the second mode of operation and the reset signal is asserted.

Claim 20

The method of claim 15 further comprising the steps of: communicating the external address value, the external data value, the external control value, the reset signal, and the system clock signal using a plurality of integrated circuit terminals; communicating the first information value using the plurality of integrated circuit terminals when the data processing system is in the first mode of operation; and communicating the internal conditioned clock signal using the plurality of integrated circuit terminals when the data processing system is in the second mode of operation and reset signal is asserted.

Claim 21

The method of claim 16 further comprising the steps of: storing a divide rate value in a control register, the divide rate value indicating a relation between the system clock signal and the internal conditioned clock signal, the control register being coupled to the bus interface means for receiving the address value, the data value, the control value, and the reset signal; storing a copy of the control register in a shadow control register, the shadow control register being coupled to a first portion of the plurality of integrated circuit terminals for receiving the external data value and the external control value, the shadow control register storing a shadow divide rate; coupling a synchronization circuit to a second portion of the plurality of integrated circuit terminals for receiving the external reset signal and the system clock signal, the synchronization circuit providing a synchronization signal; coupling an emulator function circuit to the plurality of integrated circuit terminals for receiving the external data value, the external address value, the external control value, and the external reset signal for providing a write indicator circuit to indicate the divide rate value stored in the control register has been modified; and coupling a clock synthesis circuit to the shadow control register for receiving the shadow divide rate, to a second portion of the plurality of integrated circuit terminals for receiving the system clock signal, and to the synchronization circuit for receiving the synchronization signal, the clock synthesis circuit providing an external conditioned clock signal which is substantially similar to the internal conditioned clock signal.

Claim 22

The method of claim 17 wherein one of the external data value, the external address value, and the external control value is replaced by the internal conditioned clock signal when the data processing system is operating in the second mode of operation and the reset signal is asserted.

Claim 23

The method of claim 13 wherein the first information value is the address value.

Claim 24

The method of claim 13 wherein the first mode of operation is a normal mode of operation and the second mode of operation is an emulation mode of operation.

Claim 25

The method of claim 13 wherein the internal conditioned clock signal is provided by the bus control means when the data processing system is in the second mode of operation and when the reset signal is asserted.

Claim 26

A data processing system, comprising: bus interface means for communicating a reset signal; a system clock circuit for communicating a system clock signal; a simulation clock generator coupled to the system clock circuit for receiving the system clock signal, the simulation clock generator providing an internal conditioned signal in response to the system clock signal; mode control means for determining a mode of operation of the data processing system, the mode control means providing a mode signal in a first logic state when the data processing system is operating in a first mode of operation and providing the mode signal in a second logic state when the data processing system is operating in a second mode of operation; and bus control means for providing a first information value when the data processing system is in the first mode of operation and for providing the internal conditioned signal when the data processing system is in the second mode of operation and the reset signal is asserted, the bus control means being coupled to the bus interface means for receiving the reset signal, being coupled to the mode control means for receiving the mode signal, and being coupled to the simulation clock generator for receiving the internal conditioned signal.

Claim 27

A data processing system, comprising: bus interface means for communicating a reset signal; a system clock circuit for communicating a system clock signal; a simulation clock generator coupled to the system clock circuit for receiving the system clock signal, the simulation clock generator providing an internal conditioned signal in response to the system clock signal; mode control means for determining a mode of operation of the data processing system, the mode control means providing a mode signal in a first logic state when the data processing system is operating in a first mode of operation and providing the mode signal in a second logic state when the data processing system is operating in a second mode of operation; and bus control means for providing a first information value when the data processing system is in the first mode of operation and for providing the internal conditioned signal when the data processing system is in the second mode of operation and the reset signal is asserted, the bus control means being coupled to the bus interface means for receiving the reset signal, being coupled to the mode control means for receiving the mode signal, and being coupled to the simulation clock generator for receiving the internal conditioned signal.