Voltage spike detection circuit for use in detecting clock edge transitions within a serial communication system

Claim 2

A voltage spike detection circuit for use in detecting clock edge transitions within a serial communication system comprising: a voltage change detection circuit having an input coupled to a serial communication clock of the serial communication system, and an output, the voltage change detection circuit detecting clock edge transitions of the serial communication clock; a first plurality of series-coupled latch circuits, said first plurality of series-coupled latch circuits having a first input coupled to the output of the voltage change detection circuit, a second input for receiving a first reference clock, a third input coupled to an inversion of the first reference clock, and an output; a second plurality of series-coupled latch circuits, said second plurality of series-coupled latch circuits having a first input coupled to the output of the voltage change detection circuit, a second input for receiving a second reference clock, a third input coupled to an inversion of the second reference clock, and an output; a logic gate having a first and a second input respectively coupled to the output of the first and second pluralities of series-coupled latch circuits, the logic gate having an output for indicating detecting if the output of either the first or the second plurality of series-coupled latch circuits is active; and storage means having an input coupled to the output of the logic gate, the storage means latching a predetermined logic state of the logic gate and having an output for providing an interrupt signal to the serial communication system.

Claim 3

The voltage spike detection circuit of claim 1 wherein said storage means further comprises a set/reset latch having a reset input coupled to a reset signal provided by the serial communication system, the reset signal forcing the output of the storage means to a first predetermined logic state, and having a set input coupled to the output of the logic gate, the output of logic gate forcing the output of the storage means to a second predetermined logic state.

Claim 4

The voltage spike detection circuit of claim 1 wherein the voltage change detection circuit further comprises: a second logic gate having a first input coupled to the serial communication clock, a second input, and an output for providing an edge detect signal; an odd number of logic state inverting circuits, including a single logic state inverting circuit, coupled between the serial communication clock and the second input of the second logic gate for providing a delayed inversion of the serial communication clock to the second input, the edge detect signal having a pulse width which is determined by the odd number and a gate delay associated with the second logic gate.

Claim 5

The voltage spike detection circuit of claim 1 wherein the first logic gate of the voltage change detection circuit performs a logical OR function.

Claim 6

The voltage spike detection circuit of claim 1 wherein the second logic gate of the voltage change detection circuit performs an exclusive NOR logical function.

Claim 7

The voltage spike detection circuit of claim 1 wherein each latch circuit of the first and second pluralities of series-coupled latch circuits is interconnected by first and second series-connected transistors, the first transistor having a control electrode connected to either the first or the second reference clock, the second transistor having a control electrode connected to a predetermined logic state of the output of the voltage change detection circuit, and a third transistor connected to the second transistor for selectively connecting a latch input of a predetermined latch circuit to a first power supply voltage terminal, the latch input of a first latch circuit of each of the first and second pluralities of latch circuits being connected by the first and second series-connected transistors to a second power supply voltage terminal.

Claim 8

A voltage spike detection circuit for use in detecting clock edge transitions within a serial communication system comprising: a voltage change detection circuit having an input coupled to a serial communication clock of the serial communication system, and an output, the voltage change detection circuit providing an output which transitions in logic state in response to detecting an edge transition of the serial communication clock; a first plurality of series-coupled latch circuits, said first plurality of series-coupled latch circuits having a first input coupled to the output of the voltage change detection circuit, a second input for receiving a first reference clock, a third input coupled to an inversion of the first reference clock, and selectively provides an active output indicating detection of a voltage spike on the serial communication clock; a second plurality of series-coupled latch circuits, said second plurality of series-coupled latch circuits having a first input coupled to the output of the voltage change detection circuit, a second input for receiving a second reference clock, a third input coupled to an inversion of the second reference clock, and selectively provides an active output also indicating detection of a voltage spike on the serial communication clock; and output means coupled to the output of the first and second pluralities of series-coupled latch circuits, said output means detecting if the output of either the first or the second plurality of series-coupled latch circuits is active, the output means storing and providing a predetermined logic state as an interrupt signal to the serial communication system in response to the detecting.

Claim 9

A voltage spike detection circuit for use in detecting clock edge transitions within a serial communication system comprising: a voltage change detection circuit having an input coupled to a serial communication clock of the serial communication system, and an output, the voltage change detection circuit providing an output which transitions in logic state in response to detecting an edge transition of the serial communication clock; a first plurality of series-coupled latch circuits, said first plurality of series-coupled latch circuits having a first input coupled to the output of the voltage change detection circuit, a second input for receiving a first reference clock, a third input coupled to an inversion of the first reference clock, and selectively provides an active output indicating detection of a voltage spike on the serial communication clock; a second plurality of series-coupled latch circuits, said second plurality of series-coupled latch circuits having a first input coupled to the output of the voltage change detection circuit, a second input for receiving a second reference clock, a third input coupled to an inversion of the second reference clock, and selectively provides an active output also indicating detection of a voltage spike on the serial communication clock; and output means coupled to the output of the first and second pluralities of series-coupled latch circuits, said output means detecting if the output of either the first or the second plurality of series-coupled latch circuits is active, the output means storing and providing a predetermined logic state as an interrupt signal to the serial communication system in response to the detecting.

Claim 10

The voltage spike detection circuit of claim 7 wherein the voltage change detection circuit further comprises: a logic gate having a first input coupled to the serial communication clock, a second input, and an output for providing an edge detect signal; and an odd number of logic state inverting circuits, including a single logic state inverting circuit, coupled between the serial communication clock and the second input of the logic gate for providing a delayed inversion of the serial communication clock to the second input, the edge detect signal having a pulse width which is determined by the odd number and a gate delay associated with the second logic gate.

Claim 13

The method of claim 9 wherein the step of detecting clock edge transitions of the serial communication clock further comprises the steps of: coupling the serial communication clock to a first input of circuitry which implements a logical exclusive NOR function; and delaying coupling the serial communication clock to a second input of the circuitry to provide a delayed inversion of the serial communication clock to the second input, the detect signal having a pulse width which is determined by an amount of time associated with the delayed coupling and by a gate delay associated with the circuitry which implements the logical exclusive NOR function.