US5036221A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Circuit for eliminating metastable events associated with a data signal asynchronous to a clock signal
Assignee: Texas Instruments Inc
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Filing: 1989-03-31
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Granted: 1991-07-30
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Expires: 2009-03-31
Abstract
Abstract A circuit for reducing the metastable events produced by a data signal asynchronous to a system clock signal is provided. The circuit includes an edge detector (32) for detecting a transistion of the data signal. The edge detector (32) controls a clock disable/reenable circuit (46) which will disable a system clock directed to a clocked device (36). The period of disablement is the minimum setup time for the clocked device (36). After the minimum setup time has passed, the disable/reenable circuit (42) will reenable the system clock to the clocked device (36). The system clock may be modified by a duration limit circuit (68). Data directed to the clocked device (36) may be delayed via a delay circuit (70).
Inventors
- 👤 Louis S. Brucculeri
- 👤 James N. Giddings
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 22:19
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/125; H03K5/1252
Claims Analysis
Total Claims: 19
Claim 1
Independent Claim
110 words
A circuit for reducing the metastable events in a clocked circuit produced by a data signal asynchronous with respect to a system clock signal input to the clocked circuit, comprising: a data line coupled to the clocked circuit for inputting a data signal; an edge detecting circuit coupled to the data line for detecting a transition in the data signal; a system clock for generating a system clock signal; and a disabling circuit coupled to the system clock, the edge detecting circuit and the clocked circuit for disabling the system clock signal from the clocked circuit for a predetermined time period following detection of said transition of the data signal.
Claim 2
Dependent Claim
110 words
A circuit for reducing the metastable events in a clocked circuit produced by a data signal asynchronous with respect to a system clock signal input to the clocked circuit, comprising: a data line coupled to the clocked circuit for inputting a data signal; an edge detecting circuit coupled to the data line for detecting a transition in the data signal; a system clock for generating a system clock signal; and a disabling circuit coupled to the system clock, the edge detecting circuit and the clocked circuit for disabling the system clock signal from the clocked circuit for a predetermined time period following detection of said transition of the data signal.
Claim 3
Dependent Claim
23 words
The circuit of claim 1 wherein the disabling circuit reenables the system clock signal to the clocked circuit after said predetermined time period.
Claim 4
Dependent Claim
71 words
The circuit of claim 1 wherein said detecting circuit includes: a first toggle flip flop, having an input coupled to the data line and an output coupled to the disabling circuit, for detecting a positive transition of the data signal; and a second toggle flip flop, having an input coupled to the data line and an output coupled to the disabling circuit, for detecting a negative transition of the data signal.
Claim 5
Dependent Claim
31 words
The circuit of claim 1 including a duration circuit coupled to the system clock and the disabling circuit for limiting the active period of the system clock to the clocked circuit.
Claim 6
Dependent Claim
14 words
The circuit of claim 4 wherein said duration circuit comprises a one shot circuit.
Claim 7
Dependent Claim
29 words
The circuit of claim 1 wherein the clocked circuit has a minimum setup time, and wherein said predetermined time period equals the minimum setup time of the clocked device.
Claim 8
Dependent Claim
39 words
The circuit of claim 6 including a delay circuit coupled to the data line and the clocked circuit for delaying the data signal for a predetermined delay time prior to transfer of the data signal to the clocked circuit.
Claim 9
Dependent Claim
21 words
The circuit of claim 7 wherein said predetermined delay time is greater than the propagation delay associated with said disabling circuit.
Claim 10
Dependent Claim
124 words
A circuit for reducing the metastable events in a clocked circuit produced by a data signal asynchronous with respect to a system clock signal input to the clocked circuit, comprising: a data line coupled to the clocked circuit for inputting a data signal; an edge detecting circuit coupled to the data line for detecting a transition in the data signal; a system clock for generating a system clock signal; and a disabling/reenabling circuit coupled to the system clock, the edge detecting circuit and the clocked circuit for disabling the system clock from the clocked circuit for a predetermined time period following detection of said transition of the data signal, and for reenabling the system clock to the clocked circuit following the predetermined time period.
Claim 11
Dependent Claim
124 words
A circuit for reducing the metastable events in a clocked circuit produced by a data signal asynchronous with respect to a system clock signal input to the clocked circuit, comprising: a data line coupled to the clocked circuit for inputting a data signal; an edge detecting circuit coupled to the data line for detecting a transition in the data signal; a system clock for generating a system clock signal; and a disabling/reenabling circuit coupled to the system clock, the edge detecting circuit and the clocked circuit for disabling the system clock from the clocked circuit for a predetermined time period following detection of said transition of the data signal, and for reenabling the system clock to the clocked circuit following the predetermined time period.
Claim 12
Dependent Claim
29 words
The circuit of claim 9 wherein the clocked circuit has a minimum setup time, and wherein said predetermined time period equals the minimum setup time of the clocked device.
Claim 13
Dependent Claim
27 words
The circuit of claim 9 including a duration circuit coupled to the system clock and the disable/reenable circuit for limiting an active period of the system clock.
Claim 14
Dependent Claim
31 words
The circuit of claim 10 including a delay circuit coupled to the data line and the clocked circuit for delaying the data signal prior to its receipt by the clocked circuit.
Claim 15
Independent Claim
83 words
A method of reducing the metastable events in a clocked circuit having a minimum setup time and produced by a data signal asynchronous with respect to a system clock signal input to the clocked circuit, comprising the steps of: detecting a transition of the data signal; disabling the system clock signal from the clocked circuit for a predetermined time period in response to detecting the transition; and reenabling the system clock signal to the clocked circuit following the completion of the predetermined period.
Claim 16
Independent Claim
83 words
A method of reducing the metastable events in a clocked circuit having a minimum setup time and produced by a data signal asynchronous with respect to a system clock signal input to the clocked circuit, comprising the steps of: detecting a transition of the data signal; disabling the system clock signal from the clocked circuit for a predetermined time period in response to detecting the transition; and reenabling the system clock signal to the clocked circuit following the completion of the predetermined period.
Claim 17
Dependent Claim
17 words
The method of claim 13 including the step of limiting an active period of the system clock.
Claim 18
Dependent Claim
29 words
The method of claim 13 wherein said step of disabling for a predetermined time includes disabling for a time equal to the minimum setup time of the clocked circuit.
Claim 19
Dependent Claim
47 words
The method of claim 15 including the steps of: delaying the data signal for a predetermined delay time, the delay time being greater than a propagation time for the detection and disabling steps; and transferring the data signal to the clocked circuit following the predetermined delay time.
References Cited (Backward Citations)
US3979732A
Cited
US4518865A
Cited
US4799023A
Cited
US4694196A
Cited
US4789959A
Cited
US4851710A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-07-29 | 1995-01-28 | 1995-07-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-07-29 | 1999-01-28 | 1999-07-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-07-29 | 2003-01-28 | 2003-07-30 | $7700.00 | Window Closed / Lapsed |