Circuit and method for dynamically generating a clock signal

Claim 2

An integrated circuit clock signal generator for receiving a first reference signal at a first frequency and a second reference signal at a second frequency, the integrated circuit clock signal generator providing a first clock signal, the generator further comprising: amplifier means for receiving and amplifying the first reference signal to provide an amplified signal; first logic means coupled to the amplifier means for processing the amplified signal to provide a second clock signal having a third frequency; control means having a first input for receiving the second reference signal and a second input for receiving the amplified signal, the control means processing each of the amplified signal and second reference signal to provide a first control signal; and selector means coupled to the amplifier means, the first logic means, and the control means for providing the first clock signal at either the first frequency or the third frequency in response to the first control signal.

Claim 3

The integrated circuit clock signal generator of claim 1 wherein the first control signal indicates a value of the first frequency of the first reference signal.

Claim 4

The integrated circuit clock signal generator of claim 1 wherein the amplifier means further comprises: first gain means for receiving and amplifying the first reference signal by a predetermined gain factor; and second gain means coupled to the first gain means, the second gain means selectively further amplifying the first reference signal in response to the first control signal.

Claim 5

The integrated circuit clock signal generator of claim 1 wherein the control means is further comprised of: a first detector circuit coupled to the amplifier means for detecting a presence of the amplified signal, the first detector circuit providing a second control signal to indicate the presence of the amplified signal.

Claim 6

The integrated circuit clock signal generator of claim 4 wherein the control means is further comprised of: a second divider circuit for dividing the second reference signal to provide a divided frequency signal; clock control means for providing a detect enable signal in response to the divided frequency signal and the second control signal; and a second detector circuit coupled to the clock control means for receiving the detect enable signal, the second detector circuit detecting a number of transitions of the amplified signal in response to the detect enable signal, the second detector circuit providing the first control signal in response to the number of transitions.

Claim 7

The integrated circuit clock signal generator of claim 1 wherein the first logic means is a first divider circuit, the first divider circuit dividing the amplified signal to provide the second clock signal at the third frequency.

Claim 8

The integrated circuit clock signal generator of claim 1 wherein the third frequency of the second clock signal is less than the first frequency of the first reference signal.

Claim 9

The integrated circuit clock signal generator of claim 1 further comprising: second logic means for providing an amplifier enable signal to enable the amplifier means to amplify the first reference signal by a predetermined gain factor in response to both the first control signal and a third control signal, wherein the third control signal indicates either a reset or a system start-up operation.

Claim 12

The method of claim 9 wherein the step of amplifying the reference signal further comprises the steps of: amplifying the first reference signal by a predetermined gain factor to provide an intermediate amplified signal; and selectively further amplifying the intermediate amplified signal in response to the first control signal to provide the amplified signal.

Claim 13

The method of claim 10 further comprising the steps of: detecting a presence of the amplified signal; and providing a second control signal to indicate the presence of the amplified signal.

Claim 14

The method of claim 11 further comprising the steps of: dividing the first clock signal to provide a divided frequency; providing a detect enable signal in response to the divided frequency and the second control signal; and detecting a number of transitions of the amplified signal in response the detect enable signal, the value of the first control signal being determined by the number of transitions of the amplified signal.

Claim 15

The method of claim 9 further comprising the step of: providing an amplifier enable signal to enable the amplifier means to amplify the first reference signal by a predetermined gain factor in response to both the first control signal and a third control signal, wherein the third control signal indicates either a reset or a system start-up operation.

Claim 16

The method of claim 9 wherein the step of comparing the first reference signal is further comprised of providing the first control signal to indicate a value of the second frequency of the amplified signal.

Claim 17

A phase lock loop circuit for generating a system clock signal in response to an oscillator input, comprising: a comparator having a first input for receiving a reference signal, the comparator also having a second input for receiving a divided system clock signal, the comparator providing an error signal indicating a difference between the reference signal and the divided system clock signal; a filter means for receiving the error signal and providing a first control signal; a voltage controlled oscillator means for providing the system clock signal in response to the first control signal; a divider means for dividing the system clock signal to provide the divided system clock signal to the second input of the comparator; wherein the improvement comprises a clock generator means, the clock generator means comprising: amplifier means for receiving and amplifying the oscillator input to provide an amplified signal; first logic means coupled to the amplifier means for processing the amplified signal to provide a first clock signal; control means having a first input for receiving the system clock signal and a second input for receiving the amplified signal, the control means processing each of the system clock signal and the amplified signal to provide a second control signal; and a multiplexor coupled to the amplifier means, the first logic means, and the control means for providing either the amplified signal or the first clock signal as the reference signal in response to the second control signal.

Claim 18

A phase lock loop circuit for generating a system clock signal in response to an oscillator input, comprising: a comparator having a first input for receiving a reference signal, the comparator also having a second input for receiving a divided system clock signal, the comparator providing an error signal indicating a difference between the reference signal and the divided system clock signal; a filter means for receiving the error signal and providing a first control signal; a voltage controlled oscillator means for providing the system clock signal in response to the first control signal; a divider means for dividing the system clock signal to provide the divided system clock signal to the second input of the comparator; wherein the improvement comprises a clock generator means, the clock generator means comprising: amplifier means for receiving and amplifying the oscillator input to provide an amplified signal; first logic means coupled to the amplifier means for processing the amplified signal to provide a first clock signal; control means having a first input for receiving the system clock signal and a second input for receiving the amplified signal, the control means processing each of the system clock signal and the amplified signal to provide a second control signal; and a multiplexor coupled to the amplifier means, the first logic means, and the control means for providing either the amplified signal or the first clock signal as the reference signal in response to the second control signal.

Claim 19

The phase lock loop circuit of claim 15 wherein the amplifier means further comprises: first gain means for receiving and amplifying the oscillator input by a predetermined gain factor; and second gain means coupled to the first gain means, the second gain means selectively further amplifying the oscillator input in response to the second control signal.

Claim 20

The phase lock loop circuit of claim 15 wherein the control means is further comprised of: a first detector circuit coupled to the amplifier means for detecting a presence of the amplified signal, the first detector circuit providing a third control signal to indicate the presence of the amplified signal; a second divider circuit for dividing the system clock signal to provide a divided frequency signal; clock control means for providing a detect enable signal in response to the divided frequency signal and the third control signal; and a second detector circuit coupled to the clock control means for receiving the detect enable signal, the second detector circuit detecting a number of transitions of the amplified signal in response to the detect enable signal, the second detector circuit providing the second control signal in response to the number of transitions.

Claim 21

The phase lock loop circuit of claim 15 wherein the second control signal indicates a frequency of the amplified signal.

Claim 22

The phase lock loop circuit of claim 15 wherein the first logic means is a first divider circuit, the first divider circuit dividing the amplified signal to provide the first clock signal.

Claim 23

The phase lock loop circuit of claim 15 further comprising: second logic means for providing an amplifier enable signal to enable the amplifier means to amplify the oscillator input by a predetermined gain factor in response to both the second control signal and a fourth control signal, wherein the fourth control signal indicates either a reset or a system start-up operation.

Claim 24

An integrated circuit clock signal generator, comprising: an oscillator having an output; an amplifier having a first input coupled to the oscillator and an output; a divider having an input coupled to the amplifier and a divided output; a clock control circuit having a first input coupled to the amplifier, a second input coupled to the divider, and a third input coupled to an external control signal, the clock control circuit having an output; a frequency detector having a first input coupled to the clock control circuit and a second input coupled to the external control signal, the frequency detector having an output; and a multiplexor having a first input coupled to the amplifier, a second input coupled to the divider, and a third input coupled to the frequency detector, the multiplexor having an output.

Claim 25

An integrated circuit clock signal generator, comprising: an oscillator having an output; an amplifier having a first input coupled to the oscillator and an output; a divider having an input coupled to the amplifier and a divided output; a clock control circuit having a first input coupled to the amplifier, a second input coupled to the divider, and a third input coupled to an external control signal, the clock control circuit having an output; a frequency detector having a first input coupled to the clock control circuit and a second input coupled to the external control signal, the frequency detector having an output; and a multiplexor having a first input coupled to the amplifier, a second input coupled to the divider, and a third input coupled to the frequency detector, the multiplexor having an output.