Integrated semiconductor memory circuit and method for its operation

Claim 1

An integrated semiconductor memory circuit, comprising: a supply voltage potential and a reference potential; bit lines each being formed of two bit line halves; word lines defining intersection points with said bit lines; one-transistor memory cells being disposed in matrix-like fashion at said intersection points, each of said memory cells having one selection transistor and one memory capacitor having an electrode; said selection transistor of each of said memory cells being connected to a respective one of said bit line halves; the electrode of said memory capacitor of each of said memory cells being connected during operation to a plate potential of a predetermined value; at least one dummy memory cell having at least one dummy memory capacitor for each respective bit line half with first and second electrodes; the first electrode of said at least one dummy memory capacitor being connected during operation to the plate potential; and devices for causing the second electrode of said at least one dummy memory capacitor of said at least one dummy memory cell to be acted upon during operation with a precharging potential having a value being 5 to 35% greater than a value of half a difference between the supply voltage potential and the reference potential.

Claim 3

A method for operating an integrated semiconductor memory circuit having a supply voltage potential and a reference potential; bit lines each being formed of two bit line halves; word lines defining intersection points with the bit lines; one-transistor memory cells being disposed in matrix-like fashion at the intersection points, each of the memory cells having one selection transistor and one memory capacitor having an electrode; the selection transistor of each of the memory cells being connected to a respective one of the bit line halves; the electrode of the memory capacitor of each of the memory cells being connected during operation to a plate potential of a predetermined value; at least one dummy memory cell having at least one dummy memory capacitor for each respective bit line half with first and second electrodes; the first electrode of the at least one dummy memory capacitor being connected during operation to the plate potential; and devices for causing the second electrode of the at least one dummy memory capacitor of the at least one dummy memory cell to be acted upon during operation with a precharging potential, which comprises: precharging the bit lines to a bit line potential, prior to a readout of data stored in memory cells; and applying the precharging potential with a value being 5 to 35% greater than a value of half a difference between the supply voltage and the reference potential to the second electrodes of the dummy memory capacitors of the dummy memory cells, in the precharging of the bit lines.

Claim 4

A method for operating an integrated semiconductor memory circuit having a supply voltage potential and a reference potential; bit lines each being formed of two bit line halves; word lines defining intersection points with the bit lines; one-transistor memory cells being disposed in matrix-like fashion at the intersection points, each of the memory cells having one selection transistor and one memory capacitor having an electrode; the selection transistor of each of the memory cells being connected to a respective one of the bit line halves; the electrode of the memory capacitor of each of the memory cells being connected during operation to a plate potential of a predetermined value; at least one dummy memory cell having at least one dummy memory capacitor for each respective bit line half with first and second electrodes; the first electrode of the at least one dummy memory capacitor being connected during operation to the plate potential; and devices for causing the second electrode of the at least one dummy memory capacitor of the at least one dummy memory cell to be acted upon during operation with a precharging potential, which comprises: precharging the bit lines to a bit line potential, prior to a readout of data stored in memory cells; and applying the precharging potential with a value being 5 to 35% greater than a value of half a difference between the supply voltage and the reference potential to the second electrodes of the dummy memory capacitors of the dummy memory cells, in the precharging of the bit lines.