Dynamic memory

Claim 2

A dynamic memory comprising: pairs of bit lines; a plurality of memory cells connected to each pair of bit lines; a plurality of word lines for selecting the memory cells; a precharging potential source for precharging said pairs of bit lines during a precharging period which precedes a data-reading period; a high-potential source; and a low-potential source; a plurality of sense amplifiers, each connected between a pair of bit lines, for detecting data during the data-reading period from a potential difference between the pair of bit lines; a first pair of dummy word lines; a second pair of dummy word lines; first capacitors, each connected between said first pair of dummy word lines, on the one hand, and the first of the corresponding pair of bit lines, on the other hand, for generating a reference potential; second capacitors, each connected between said second pair of dummy word lines, on the one hand, and the second of the corresponding pair of bit lines, on the other hand, for generating a reference potential; a first dummy word line driving circuit connected to said first pair of dummy word lines, for generating the reference potential in the first of each pair of bit lines; a second dummy word line driving circuit connected to said second pair of dummy word lines, for generating the reference potential in the second of each pair of bit lines; and a selection circuit for selecting either said first dummy word line driving circuit or said second dummy word line driving circuit, wherein during said precharging period, said first and second dummy word line driving circuits set said first and second pairs of dummy word lines at the potential of said precharging potential source, and during said data-reading period, the dummy word line driving circuit selected by said selection circuit sets the pair of dummy word lines at the potential of said high-potential source and the potential of said low-potential source, respectively, and the dummy word line driving circuit not selected by said selection circuit sets the pair of dummy word lines at the potential of said precharging potential source.

Claim 3

The dynamic memory according to claim 1, wherein said first capacitors and said second capacitors have the same capacitance.

Claim 4

The dynamic memory according to claim 1, wherein said selection circuit selects either said first dummy word line driving circuit or said second dummy word line driving circuit, in accordance with an address signal for driving said word lines.

Claim 5

The dynamic memory according to claim 1, wherein each of said dummy word line driving circuits comprises: first and second switching means connected between said pair of dummy word lines and said precharging potential source; third switching means connected between the first of said pair of dummy word lines and said high-potential source, said third switching means being turned on during said data-reading period; fourth switching means connected between the second of said pair of dummy word lines and said low-potential source, said fourth switching means being turned on during said data-reading period when selected by said selection circuit; and control means connected to receive a precharge control signal and an output signal of said selection circuit, for turning on said third and fourth switching means during said precharging period, and for turning on said first and second switching means during said data-reading period when selected by said selection circuit.

Claim 6

The dynamic memory according to claim 4, wherein said first to fourth switching means are MOS transistors.

Claim 7

The dynamic memory according to claim 4, wherein said control means comprises a gate circuit connected to receive said precharge control signal and the output of said selection circuit.

Claim 8

The dynamic memory according to claim 4, wherein each of said dummy word line driving circuits comprises: first and second switching means connected between said pair of dummy word lines and said precharging potential source; third switching means connected between the first of said pair of dummy word lines and said high-potential source, said third switching means being controlled by an output signal of said selection circuit; fourth switching means connected between the second of said pair of dummy word lines and said low-potential source, said fourth switching means being controlled by the output of said selection circuit; fifth switching means connected between the first of said pair of dummy word lines and said precharging potential source, said fifth switching means being controlled by an output signal of said selection circuit; and sixth switching means connected between the second of said pair of dummy word lines and said precharging potential source, said sixth switching means being controlled by the output of said selection circuit.

Claim 9

The dynamic memory according to claim 7, wherein said first to sixth switching means are MOS transistors.

Claim 10

The dynamic memory according to claim 4, wherein each of said first and second dummy word line driving circuits further comprises switching means connected between the pair of dummy word lines, for supplying an equalizing signal under the control of said precharge control signal.

Claim 11

The dynamic memory according to claim 7, wherein each of said first and second dummy word line driving circuits further comprises switching means connected between the pair of dummy word lines, for supplying an equalizing signal under the control of said precharge control signal.

Claim 12

The dynamic memory according to claim 1, further comprising a plurality of switching means, each connected between the pair of bit lines, for supplying an equalizing signal under the control of said precharge control signal.

Claim 13

A dynamic memory comprising: pairs of bit lines; a plurality of memory cells connected to each pair of bit lines; a plurality of word lines for selecting the memory cells; a precharging potential source for precharging said pairs of bit lines during a precharging period which precedes a data-reading period; a high-potential source; and a low-potential source; a plurality of sense amplifiers, each connected between a pair of bit lines, for detecting data during the data-reading period from a potential difference between the pair of bit lines; a first pair of dummy word lines; a second pair of dummy word lines; first capacitors, each connected between said first pair of dummy word lines, on the one hand, and the first of the corresponding pair of bit lines, on the other hand, for generating a reference potential; second capacitors, each connected between said second pair of dummy word lines, on the one hand, and the second of the corresponding pair of bit lines, on the other hand, for generating a reference potential; a first dummy word line driving circuit connected to said first pair of dummy word lines, for generating the reference potential in the first of each pair of bit lines; a second dummy word line driving circuit connected to said second pair of dummy word lines, for generating the reference potential in the second of each pair of bit lines; and a selection circuit for selecting either said first dummy word line driving circuit or said second dummy word line driving circuit, wherein each of said dummy word line driving circuits comprises: first MOS transistor connected between the first of the pair of dummy word lines and said precharging potential source; second MOS transistor connected between the second of the pair of dummy word lines and said precharging potential source; third MOS transistor connected between the first of the pair of dummy word lines and said high-potential source, said third MOS transistor being turned on during said data-reading period when selected by said selection circuit; fourth MOS transistor connected between the second of said pair of dummy word lines and said low-potential source, said fourth MOS transistor being turned on during said data-reading period when selected by said selection circuit; and a gate circuit connected to receive a precharge control signal and an output signal of said selection circuit, for turning on said first and second MOS transistors during said precharging period, and for turning on said third and fourth MOS transistors during said data-reading period when said selection circuit outputs no signals.

Claim 14

A dynamic memory comprising: pairs of bit lines; a plurality of memory cells connected to each pair of bit lines; a plurality of word lines for selecting the memory cells; a precharging potential source for precharging said pairs of bit lines during a precharging period which precedes a data-reading period; a high-potential source; and a low-potential source; a plurality of sense amplifiers, each connected between a pair of bit lines, for detecting data during the data-reading period from a potential difference between the pair of bit lines; a first pair of dummy word lines; a second pair of dummy word lines; first capacitors, each connected between said first pair of dummy word lines, on the one hand, and the first of the corresponding pair of bit lines, on the other hand, for generating a reference potential; second capacitors, each connected between said second pair of dummy word lines, on the one hand, and the second of the corresponding pair of bit lines, on the other hand, for generating a reference potential; a first dummy word line driving circuit connected to said first pair of dummy word lines, for generating the reference potential in the first of each pair of bit lines; a second dummy word line driving circuit connected to said second pair of dummy word lines, for generating the reference potential in the second of each pair of bit lines; and a selection circuit for selecting either said first dummy word line driving circuit or said second dummy word line driving circuit, wherein each of said dummy word line driving circuits comprises: first MOS transistor connected between the first of the pair of dummy word lines and said precharging potential source; second MOS transistor connected between the second of the pair of dummy word lines and said precharging potential source; third MOS transistor connected between the first of the pair of dummy word lines and said high-potential source, said third MOS transistor being turned on during said data-reading period when selected by said selection circuit; fourth MOS transistor connected between the second of said pair of dummy word lines and said low-potential source, said fourth MOS transistor being turned on during said data-reading period when selected by said selection circuit; and a gate circuit connected to receive a precharge control signal and an output signal of said selection circuit, for turning on said first and second MOS transistors during said precharging period, and for turning on said third and fourth MOS transistors during said data-reading period when said selection circuit outputs no signals.

Claim 15

The dynamic memory according to claim 12, wherein said first capacitors and said second capacitors have the same capacitance.

Claim 16

The dynamic memory according to claim 12, wherein said selection circuit selects either said first dummy word line driving circuit or said second dummy word line driving circuit, in accordance with an address signal for driving said word lines.

Claim 17

A dynamic memory comprising: a plurality of pairs of bit lines; a plurality of memory cells connected to each pair of bit lines; a plurality of word lines for selecting the memory cells; a plurality of potential source for precharging said pairs of bit lines during a precharging period which precedes a data-reading period; a high-potential source; a low-potential source; a plurality of sense amplifiers, each connected between a pair of bit lines, for detecting data during the data-reading period from a potential difference between the pair of bit lines; a first pair of dummy word lines; a second pair of dummy word lines; first capacitors, each connected between said first pair of dummy word lines and the first pair of the corresponding pair of bit lines, for generating a reference potential; second capacitors, each connected between said first second pair of dummy word lines and the second of the corresponding pair of bit lines, for generating a reference potential; a first dummy word line driving circuit connected to said first pair of dummy word lines for generating the reference potential in the first of each pair of bit lines; a second dummy word line driving circuit connected to said second pair of dummy word lines, for generating the reference potential in the second of each pair of bit lines; and a selection circuit for selecting either said first dummy word line driving circuit or said second dummy word line driving circuit, wherein each of said dummy word line driving circuits comprises: a first MOS transistor connected between the first of the pair of dummy word lines and said precharging potential source, said first MOS transistor being controlled by a precharge control signal; a second MOS transistor connected between the second of the pair of dummy word lines and said precharging potential source, said second MOS transistor being controlled by a precharge control signal; a third MOS transistor connected between the pair of dummy word lines, said third MOS transistor being controlled by the precharge control signal; a fourth MOS transistor Connected between the first of the pair of dummy word lines and said high-potential source, said fourth MOS transistor being controlled by an output of said selection circuit; a fifth MOS transistor connected between the second of said pair of dummy word lines and said low-potential source, said fifth MOS transistor being controlled by an output of said selection circuit; a sixth MOS transistor connected between the first of said pair of dummy word lines and said precharging potential source, said sixth MOS transistor being controlled by an output of said selection circuit; and a seventh MOS transistor connected between the second of said pair of dummy word lines and said precharging potential source, said seventh MOS transistor being controlled by an output of said selection circuit.

Claim 18

A dynamic memory comprising: a plurality of pairs of bit lines; a plurality of memory cells connected to each pair of bit lines; a plurality of word lines for selecting the memory cells; a plurality of potential source for precharging said pairs of bit lines during a precharging period which precedes a data-reading period; a high-potential source; a low-potential source; a plurality of sense amplifiers, each connected between a pair of bit lines, for detecting data during the data-reading period from a potential difference between the pair of bit lines; a first pair of dummy word lines; a second pair of dummy word lines; first capacitors, each connected between said first pair of dummy word lines and the first pair of the corresponding pair of bit lines, for generating a reference potential; second capacitors, each connected between said first second pair of dummy word lines and the second of the corresponding pair of bit lines, for generating a reference potential; a first dummy word line driving circuit connected to said first pair of dummy word lines for generating the reference potential in the first of each pair of bit lines; a second dummy word line driving circuit connected to said second pair of dummy word lines, for generating the reference potential in the second of each pair of bit lines; and a selection circuit for selecting either said first dummy word line driving circuit or said second dummy word line driving circuit, wherein each of said dummy word line driving circuits comprises: a first MOS transistor connected between the first of the pair of dummy word lines and said precharging potential source, said first MOS transistor being controlled by a precharge control signal; a second MOS transistor connected between the second of the pair of dummy word lines and said precharging potential source, said second MOS transistor being controlled by a precharge control signal; a third MOS transistor connected between the pair of dummy word lines, said third MOS transistor being controlled by the precharge control signal; a fourth MOS transistor Connected between the first of the pair of dummy word lines and said high-potential source, said fourth MOS transistor being controlled by an output of said selection circuit; a fifth MOS transistor connected between the second of said pair of dummy word lines and said low-potential source, said fifth MOS transistor being controlled by an output of said selection circuit; a sixth MOS transistor connected between the first of said pair of dummy word lines and said precharging potential source, said sixth MOS transistor being controlled by an output of said selection circuit; and a seventh MOS transistor connected between the second of said pair of dummy word lines and said precharging potential source, said seventh MOS transistor being controlled by an output of said selection circuit.

Claim 19

The dynamic memory according to claim 15, wherein said first capacitors and said second capacitors have the same capacitance.

Claim 20

The dynamic memory according to claim 15, wherein said selection circuit selects either said first dummy word line driving circuit or said second dummy word line driving circuit in accordance with an address signal used for driving said word lines.