Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
233 words
A dynamic type random-access memory comprising: a bit line pair constituted by first and second bit lines (BL, BL ); a memory cell array constituted by a plurality of memory cells (MC i : i = 0 to 255) connected to said bit line pair; a precharge circuit (PR) for precharging said bit line pair to a predetermined potential at a predetermined timing; a bit line sense amplifier (NA, PA) to be enabled after data written in one of said plurality of memory cells (MCi: i = 0 to 255) is read out to said bit line pair; and a charge transfer circuit (NT₁, NT₂, PT₁, PT₂, S, D) connected between said bit line pair and first and second sense nodes (SN, SN ) of said bit line sense amplifier (NA, PA), turned off upon reception of a charge transfer drive signal when a small potential difference is produced between bit lines of said bit line pair, and having an impedance decreased as a potential difference between said bit line pair and said first and second sense nodes (SN, SN ) of said bit line sense amplifier (NA, PA) is increased when a potential difference between a control terminal and said first and second sense nodes (SN, SN ) or a potential difference between one of said bit line pair and one of said first and second sense nodes exceeds a threshold value.
Claim 2
Dependent Claim
233 words
A dynamic type random-access memory comprising: a bit line pair constituted by first and second bit lines (BL, BL ); a memory cell array constituted by a plurality of memory cells (MC i : i = 0 to 255) connected to said bit line pair; a precharge circuit (PR) for precharging said bit line pair to a predetermined potential at a predetermined timing; a bit line sense amplifier (NA, PA) to be enabled after data written in one of said plurality of memory cells (MCi: i = 0 to 255) is read out to said bit line pair; and a charge transfer circuit (NT₁, NT₂, PT₁, PT₂, S, D) connected between said bit line pair and first and second sense nodes (SN, SN ) of said bit line sense amplifier (NA, PA), turned off upon reception of a charge transfer drive signal when a small potential difference is produced between bit lines of said bit line pair, and having an impedance decreased as a potential difference between said bit line pair and said first and second sense nodes (SN, SN ) of said bit line sense amplifier (NA, PA) is increased when a potential difference between a control terminal and said first and second sense nodes (SN, SN ) or a potential difference between one of said bit line pair and one of said first and second sense nodes exceeds a threshold value.
Claim 3
Dependent Claim
122 words
A memory according to claim 1, characterized in that said charge transfer circuit (NT₁, NT₂, PT₁, PT₂, S, D) has an impedance which changes when a potential difference between a first terminal of said first and second bit lines (BL, BL ) and a second terminal of said first and second sense nodes (SN, SN ) changes, is turned off when a potential difference between a third terminal and one of said first and second terminals becomes not less than a predetermined value, and is temporarily turned off when a small potential difference is produced between said first and second bit lines (BL, BL ) upon reading out of data from said memory cell (MC i : i = 0 to 255).
Claim 4
Dependent Claim
40 words
A memory according to claim 1, characterized in that said charge transfer circuit is a field effect transistor (NT₁, NT₂, PT₁, PT₂), a predetermined drive signal being supplied to the gate of said field effect transistor (NT₁, NT₂, PT₁, PT₂).
Claim 5
Dependent Claim
81 words
A memory according to claim 1, characterized in that said field effect transistor is an n-channel MOS transistor (NT₁, NT₂), the level of a drive signal to be supplied to the gate of said MOS transistor (NT₁, NT₂) being decreased from the power source potential to the medium potential between the power source potential and the ground potential in order to turn off said MOS transistor (NT₁, NT₂) and being increased in order to turn on said MOS transistor (NT₁, NT₂).
Claim 6
Dependent Claim
79 words
A memory according to claim 1, characterized in that said field effect transistor is a p-channel MOS transistor (PT₁, PT₂), the level of drive signal to be supplied to the gate of said MOS transistor (PT₁, PT₂) being increased from the ground potential to the medium potential between the power source potential and the ground potential in order to turn off said MOS transistor (PT₁, PT₂) and being decreased in order to turn on said MOS transistor (PT₁, PT₂).
Claim 7
Dependent Claim
36 words
A memory according to claim 1, characterized in that said charge transfer circuit is constituted by connecting a diode (D) and a switch circuit (S) in parallel with each other, said switch circuit (S) being switching-driven.