Method for making dynamic random access memory with fin-type stacked capacitor

Claim 1

A method for fabricating a dynamic random access memory having a high capacitance stacked capacitor comprising: selectively forming relatively thick field oxide areas on the surface of a semiconductor substrate while leaving device areas for fabrication of field effect devices; forming a gate dielectric layer on said substrate in the said device areas; depositing a relatively thick first layer of polysilicon on the said field oxide areas and said device areas; removing portions of said first polysilicon layer while leaving portions thereof for the gate structure in said device areas, and portions over said field oxide areas; forming source/drain structures within said device areas of said semiconductor substrate associated with said gate structures; forming a first insulator layer composed at least in part of silicon nitride over said device and field oxide areas and patterning the layer to leave source/drain structures open in the said device areas where electrical contact is desired to said stacked capacitors; and forming said stacked capacitors by, depositing a second polysilicon layer over the device and field oxide areas, depositing a second insulator layer over said second polysilicon layer, depositing a third polysilicon layer over the second insulator layer, depositing a third insulator layer over said third polysilicon layer, depositing a fourth polysilicon layer over said third insulator layer, patterning and anisotropical etching the stack of said second and third insulators layers, and said second, third and fourth polysilicon layers to form the basis of said stacked capacitor, controlably and laterally isotropic etching the exposed edges of said second and third insulator layers to increase the planned surface area of the capacitor while leaving a central portion of said second and third insulator layers, depositing a fifth polysilicon layer over the device and field oxide areas to complete the lower electrode of said stacked capacitor, forming a capacitor dielectric layer over the said lower electrode of said stacked capacitor, and depositing a top polysilicon electrode layer to complete said stacked capacitors.

Claim 2

A method for fabricating a dynamic random access memory having a high capacitance stacked capacitor comprising: selectively forming relatively thick field oxide areas on the surface of a semiconductor substrate while leaving device areas for fabrication of field effect devices; forming a gate dielectric layer on said substrate in the said device areas; depositing a relatively thick first layer of polysilicon on the said field oxide areas and said device areas; removing portions of said first polysilicon layer while leaving portions thereof for the gate structure in said device areas, and portions over said field oxide areas; forming source/drain structures within said device areas of said semiconductor substrate associated with said gate structures; forming a first insulator layer composed at least in part of silicon nitride over said device and field oxide areas and patterning the layer to leave source/drain structures open in the said device areas where electrical contact is desired to said stacked capacitors; and forming said stacked capacitors by, depositing a second polysilicon layer over the device and field oxide areas, depositing a second insulator layer over said second polysilicon layer, depositing a third polysilicon layer over the second insulator layer, depositing a third insulator layer over said third polysilicon layer, depositing a fourth polysilicon layer over said third insulator layer, patterning and anisotropical etching the stack of said second and third insulators layers, and said second, third and fourth polysilicon layers to form the basis of said stacked capacitor, controlably and laterally isotropic etching the exposed edges of said second and third insulator layers to increase the planned surface area of the capacitor while leaving a central portion of said second and third insulator layers, depositing a fifth polysilicon layer over the device and field oxide areas to complete the lower electrode of said stacked capacitor, forming a capacitor dielectric layer over the said lower electrode of said stacked capacitor, and depositing a top polysilicon electrode layer to complete said stacked capacitors.

Claim 10

A method for fabricating a high capacitance stacked capacitor comprising: selectively forming relatively thick field oxide areas on the surface of a semiconductor substrate while leaving device areas for fabrication of semiconductor devices; forming device structures within said device areas of said semiconductor substrate; forming a first insulator layer composed at least in part of silicon nitride over said device and field oxide areas and patterning the layer to leave device structures open in the said device areas where electrical contact is desired to said stacked capacitors; and forming said stacked capacitors by, depositing alternating layers of polysilicon and insulator over the device and field oxide areas with a first polysilicon layer being contact to the said device areas for electrical contact and the last polysilicon layer being the topmost of said alternating layers, patterning and anisotropical etching the stack of said alternating polysilicon and insulator layers to form the basis of said stacked capacitor, controlably and laterally isotropic etching the exposed edges of said insulator layers to increase the planned surface area of the capacitor while leaving a central portion of said second and third insulator layers, depositing an in situ doped polysilicon layer over the device and field oxide areas to complete the lower electrode of said stacked capacitor, forming a capacitor dielectric layer over the said lower electrode of said stacked capacitor, and depositing a top polysilicon electrode layer to complete said stacked capacitors.

Claim 11

A method for fabricating a high capacitance stacked capacitor comprising: selectively forming relatively thick field oxide areas on the surface of a semiconductor substrate while leaving device areas for fabrication of semiconductor devices; forming device structures within said device areas of said semiconductor substrate; forming a first insulator layer composed at least in part of silicon nitride over said device and field oxide areas and patterning the layer to leave device structures open in the said device areas where electrical contact is desired to said stacked capacitors; and forming said stacked capacitors by, depositing alternating layers of polysilicon and insulator over the device and field oxide areas with a first polysilicon layer being contact to the said device areas for electrical contact and the last polysilicon layer being the topmost of said alternating layers, patterning and anisotropical etching the stack of said alternating polysilicon and insulator layers to form the basis of said stacked capacitor, controlably and laterally isotropic etching the exposed edges of said insulator layers to increase the planned surface area of the capacitor while leaving a central portion of said second and third insulator layers, depositing an in situ doped polysilicon layer over the device and field oxide areas to complete the lower electrode of said stacked capacitor, forming a capacitor dielectric layer over the said lower electrode of said stacked capacitor, and depositing a top polysilicon electrode layer to complete said stacked capacitors.