Method of making semiconductor memory device having stacked capacitor

Claim 1

A method of producing a semiconductor memory device which includes a substrate, a transfer transistor formed on said substrate and a charge storage capacitor electrically coupled to one of drain and source regions of said transfer transistor, said method comprising the steps of: alternately forming first and second layers a plurality of times on an insulator layer which is formed on said substrate to form a stacked structure above said one of the drain and source regions of said transfer transistor, at least said first layers being made of a conductive material, a lowermost one of said first layers being electrically coupled to said one of the drain and source regions of said transfer transistor via a contact hole in said insulator layer; patterning said stacked structure to have a side at a position avoiding said contact hole; forming at least one side wall on said side of said stacked structure at said position avoiding said contact hole, said side wall being made of a conductive material and forming a storage electrode of said charge storage capacitor together with said first layers; removing the second layers of said stacked structure without removing said first layers immediately above said contact hole; forming a dielectric layer on exposed surfaces of said first layers and said side wall; and forming a conductor layer on a surface of said dielectric layer to form an opposed electrode of said charge storage capacitor.

Claim 2

A method of producing a semiconductor memory device which includes a substrate, a transfer transistor formed on said substrate and a charge storage capacitor electrically coupled to one of drain and source regions of said transfer transistor, said method comprising the steps of: alternately forming first and second layers a plurality of times on an insulator layer which is formed on said substrate to form a stacked structure above said one of the drain and source regions of said transfer transistor, at least said first layers being made of a conductive material, a lowermost one of said first layers being electrically coupled to said one of the drain and source regions of said transfer transistor via a contact hole in said insulator layer; patterning said stacked structure to have a side at a position avoiding said contact hole; forming at least one side wall on said side of said stacked structure at said position avoiding said contact hole, said side wall being made of a conductive material and forming a storage electrode of said charge storage capacitor together with said first layers; removing the second layers of said stacked structure without removing said first layers immediately above said contact hole; forming a dielectric layer on exposed surfaces of said first layers and said side wall; and forming a conductor layer on a surface of said dielectric layer to form an opposed electrode of said charge storage capacitor.

Claim 4

A method of producing a semiconductor memory device which includes a substrate, a transfer transistor formed on said substrate and a charge storage capacitor electrically coupled to one of drain and source regions of said transfer transistor, said method comprising the steps of: successively forming a gate insulator layer, a word line and a first interlayer insulator on said substrate, said word line being located above the other of the drain and source regions of said transfer transistor; forming first and second contact holes in said first interlayer insulator and said gate insulator layer respectively above said one and said other of the drain and source regions of said transfer transistor; alternately forming first and second layers a plurality of times on said first interlayer insulator, at least said first layers being made of a conductive material, a lowermost one of said first layers being electrically coupled to the drain and source regions of said transfer transistor via said first and second contact holes; patterning said first and second layers to form first and second stacked structures respectively above said first and second contact holes; forming at least one side wall on a side of each of said first and second stacked structures, said side wall being made of a conductive material, said side wall on said first stacked structure forming a storage electrode of said charge storage capacitor together with said first layers; removing the second layers of said first stacked structure; forming a dielectric layer on exposed surfaces of said first layers of said first stacked structure and said side wall on said first stacked structure; forming a first conductor layer on a surface of said dielectric layer to form an opposed electrode of said charge storage capacitor; forming a second interlayer insulator on said first conductor layer; forming a third contact hole in said second interlayer insulator to a top surface of said second stacked structure; and forming a second conductor layer on said second interlayer insulator, said second conductor layer forming a bit line and being electrically coupled to said other of the drain and source regions of said transfer transistor via said third contact hole, said second stacked structure and said second contact hole.

Claim 5

A method of producing a semiconductor memory device which includes a substrate, a transfer transistor formed on said substrate and a charge storage capacitor electrically coupled to one of drain and source regions of said transfer transistor, said method comprising the steps of: successively forming a gate insulator layer, a word line and a first interlayer insulator on said substrate, said word line being located above the other of the drain and source regions of said transfer transistor; forming first and second contact holes in said first interlayer insulator and said gate insulator layer respectively above said one and said other of the drain and source regions of said transfer transistor; alternately forming first and second layers a plurality of times on said first interlayer insulator, at least said first layers being made of a conductive material, a lowermost one of said first layers being electrically coupled to the drain and source regions of said transfer transistor via said first and second contact holes; patterning said first and second layers to form first and second stacked structures respectively above said first and second contact holes; forming at least one side wall on a side of each of said first and second stacked structures, said side wall being made of a conductive material, said side wall on said first stacked structure forming a storage electrode of said charge storage capacitor together with said first layers; removing the second layers of said first stacked structure; forming a dielectric layer on exposed surfaces of said first layers of said first stacked structure and said side wall on said first stacked structure; forming a first conductor layer on a surface of said dielectric layer to form an opposed electrode of said charge storage capacitor; forming a second interlayer insulator on said first conductor layer; forming a third contact hole in said second interlayer insulator to a top surface of said second stacked structure; and forming a second conductor layer on said second interlayer insulator, said second conductor layer forming a bit line and being electrically coupled to said other of the drain and source regions of said transfer transistor via said third contact hole, said second stacked structure and said second contact hole.