Patent US5568060A successfully refreshed from Google Patents.
US5568060A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Circuit board insertion circuitry for high reliability backplanes
Assignee: F Poszat HU LLC
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Filing: 1995-07-20
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Granted: 1996-10-22
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Expires: 2015-07-20
Abstract
Abstract Circuit board insertion circuitry is used in conjunction with a staggered electrical connector. The insertion circuitry includes an isolated circuit which receives a high system voltage upon first stage contact between the card and a high voltage bus, and uses that high system voltage to tristate the output of a transceiver on the circuit board prior to second stage contact being made between the transceiver and the backplane data bus. Override circuitry for overriding the tristating effects of the isolating circuit are provided such that when the bias circuit which controls the transceiver output is properly powered, the bias circuit will control the transceiver output, and not the isolated circuit. Additional circuitry which isolates the circuit board so that a power fault on the board will not impact other boards on the backplane is also provided. The additional circuitry preferably includes a relative large resistor and a Schottky diode which are provided in parallel between a 5 V bus and the protection diodes of the transceiver.
Inventors
- 👤 William G. Bartholomay
- 👤 Eugene L. Parrella
- 👤 Daniel C. Upp
- 👤 Mikio S. Ichiba
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 18:58
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/0175; H03K19/0185; H03K19/018557; H03K19/02; H03K19/08; H03K19/094; H03K19/09425; H03K19/09429
Claims Analysis
Total Claims: 22
Claim 1
Independent Claim
248 words
Apparatus on a circuit board for temporarily controlling the output of a transceiver on the circuit board which is otherwise controlled by a bias circuit and which is to be coupled to an open drain data bus, the apparatus being used in conjunction with a staggered electrical connector which first connects the circuit board to a high system voltage rail and then to the open drain data bus, said apparatus comprising: a) an isolated circuit means on the circuit board, with the isolated circuit means being coupled to the high system voltage rail upon connection of the circuit board to the high system voltage rail, and also being coupled to the transceiver, said isolated circuit means for controlling the output of the transceiver by quickly receiving a high system voltage from the high system voltage rail upon connection of the circuit board to the high system voltage rail, and by using said high system voltage in order to tristate the output of the transceiver within at most one millisecond after the staggered electrical connector connects the circuit board to the high system voltage rail, and prior to the staggered electrical connector being connecting to the data bus; and b) tristate override means for turning off control of the transceiver by said isolation circuit means after the electrical connector connects the transceiver on the circuit board to the open drain data bus, and after the bias circuit is fully powered so that it can properly control the transceiver output.
Claim 2
Dependent Claim
248 words
Apparatus on a circuit board for temporarily controlling the output of a transceiver on the circuit board which is otherwise controlled by a bias circuit and which is to be coupled to an open drain data bus, the apparatus being used in conjunction with a staggered electrical connector which first connects the circuit board to a high system voltage rail and then to the open drain data bus, said apparatus comprising: a) an isolated circuit means on the circuit board, with the isolated circuit means being coupled to the high system voltage rail upon connection of the circuit board to the high system voltage rail, and also being coupled to the transceiver, said isolated circuit means for controlling the output of the transceiver by quickly receiving a high system voltage from the high system voltage rail upon connection of the circuit board to the high system voltage rail, and by using said high system voltage in order to tristate the output of the transceiver within at most one millisecond after the staggered electrical connector connects the circuit board to the high system voltage rail, and prior to the staggered electrical connector being connecting to the data bus; and b) tristate override means for turning off control of the transceiver by said isolation circuit means after the electrical connector connects the transceiver on the circuit board to the open drain data bus, and after the bias circuit is fully powered so that it can properly control the transceiver output.
Claim 3
Dependent Claim
68 words
An apparatus according to claim 1, where the transceiver comprises a first MOS transistor having a drain coupled to the data bus, a gate coupled to the bias circuit, and a source coupled to ground, wherein: said isolated circuit means comprises a second MOS transistor means coupled to the gate of the first MOS transistor, said second MOS transistor means for temporarily turning said first MOS transistor OFF.
Claim 4
Dependent Claim
45 words
An apparatus according to claim 2, wherein: said isolated circuit means further comprises a buffer means which turns on upon receiving said high system voltage, said buffer means for providing a signal of a first value to a gate of said second MOS transistor means.
Claim 5
Dependent Claim
64 words
An apparatus according to claim 3, wherein: said second MOS transistor means has a source coupled to ground and a drain coupled to the gate of the first MOS transistor, and said buffer means is an inverting buffer which receives a guaranteed low input upon power up, and provides a high signal upon power up to said gate of said second MOS transistor means.
Claim 6
Dependent Claim
61 words
An apparatus according to claim 2, wherein: said tristate override means comprises means for preventing said second MOS transistor means from turning the first MOS transistor OFF after the electrical connector connects the transceiver on the circuit board to the open drain data bus, and after the bias circuit is fully powered so that it can properly control the transceiver output.
Claim 7
Dependent Claim
61 words
An apparatus according to claim 3, wherein: said tristate override means comprises means for preventing said second MOS transistor means from turning the first MOS transistor OFF after the electrical connector connects the transceiver on the circuit board to the open drain data bus, and after the bias circuit is fully powered so that it can properly control the transceiver output.
Claim 8
Dependent Claim
46 words
An apparatus according to claim 6, wherein: said means for preventing comprises a logic control means coupled to said buffer means, said logic control means for causing said buffer means to change its output to a signal of a second value different than said first value.
Claim 9
Dependent Claim
94 words
An apparatus according to claim 1, further comprising: c) a circuit board bus which is coupled by the staggered electrical connector to the high system voltage rail, wherein said isolated circuit means comprises a diode which is coupled in series in said circuit board bus, such that all connections between said circuit board bus and elements of the circuit board requiring power from said circuit board bus other than said isolated circuit means are located at locations along said circuit board bus which are other than between said diode and said staggered electrical connector.
Claim 10
Dependent Claim
95 words
An apparatus according to claim 4, further comprising: c) a circuit board bus which is coupled by the staggered electrical connector to the high system voltage rail, wherein said isolated circuit means further comprises a diode which is coupled in series in said circuit board bus, such that all connections between said circuit board bus and elements of the circuit board requiring power from said circuit board bus other than said isolated circuit means are located at locations along said circuit board bus which are other than between said diode and said staggered electrical connector.
Claim 11
Dependent Claim
80 words
An apparatus according to claim 1, further comprising: c) a circuit board bus which is coupled by the staggered electrical connector to the high system voltage rail; and d) circuit means for preventing a large current flow from the data bus through to said circuit board bus should a failure on the circuit board cause said circuit board bus to be pulled to a low voltage, which large current flow would pull the data bus down to a low voltage.
Claim 12
Dependent Claim
22 words
An apparatus according to claim 10, wherein: said circuit means comprises a resistor coupled between said circuit board bus and the transceiver.
Claim 13
Dependent Claim
20 words
An apparatus according to claim 11, wherein: said circuit means further comprises a diode coupled in parallel with said resistor.
Claim 14
Dependent Claim
13 words
An apparatus according to claim 12, wherein: said diode is a Schottky diode.
Claim 15
Dependent Claim
60 words
An apparatus according to claim 9, further comprising: d) circuit means for preventing a large current flow from the data bus through to said circuit board bus should a failure on the circuit board cause said circuit board bus to be pulled to a low voltage, which large current flow would pull the data bus down to a low voltage.
Claim 16
Dependent Claim
22 words
An apparatus according to claim 14, wherein: said circuit means comprises a resistor coupled between said circuit board bus and the transceiver.
Claim 17
Dependent Claim
21 words
An apparatus according to claim 15, wherein: said circuit means further comprises a second diode coupled in parallel with said resistor.
Claim 18
Dependent Claim
14 words
An apparatus according to claim 16, wherein: said second diode is a Schottky diode.
Claim 19
Independent Claim
248 words
An apparatus on a circuit board which is to be used in conjunction with a staggered electrical connector which first connects the circuit board to a high system voltage rail and then to an open drain data bus, said apparatus comprising: a) a transceiver including a driving MOS transistor which is coupled to the open drain data bus, a bias circuit means for controlling said driving MOS transistor, and a receiver coupled to the open drain data bus; b) an isolated circuit means which is coupled to the high system voltage rail upon connection of the circuit board to the high system voltage rail, and also being coupled to said transceiver, said isolated circuit means for temporarily controlling an output of said transceiver by quickly receiving a high system voltage from the high system voltage rail upon connection of the circuit board to the high system voltage rail, and by using said high system voltage in order to tristate the output of said transceiver within at most one millisecond after the staggered electrical connector connects the circuit board to the high system voltage rail, and prior to the staggered electrical connector being connecting to the data bus; and c) tristate override means for turning off control of said transceiver by said isolation circuit means after the electrical connector connects said transceiver on the circuit board to the open drain data bus, and after the bias circuit is fully powered so that it can properly control said transceiver output.
Claim 20
Independent Claim
248 words
An apparatus on a circuit board which is to be used in conjunction with a staggered electrical connector which first connects the circuit board to a high system voltage rail and then to an open drain data bus, said apparatus comprising: a) a transceiver including a driving MOS transistor which is coupled to the open drain data bus, a bias circuit means for controlling said driving MOS transistor, and a receiver coupled to the open drain data bus; b) an isolated circuit means which is coupled to the high system voltage rail upon connection of the circuit board to the high system voltage rail, and also being coupled to said transceiver, said isolated circuit means for temporarily controlling an output of said transceiver by quickly receiving a high system voltage from the high system voltage rail upon connection of the circuit board to the high system voltage rail, and by using said high system voltage in order to tristate the output of said transceiver within at most one millisecond after the staggered electrical connector connects the circuit board to the high system voltage rail, and prior to the staggered electrical connector being connecting to the data bus; and c) tristate override means for turning off control of said transceiver by said isolation circuit means after the electrical connector connects said transceiver on the circuit board to the open drain data bus, and after the bias circuit is fully powered so that it can properly control said transceiver output.
Claim 21
Dependent Claim
121 words
An apparatus according to claim 18, wherein: said driving MOS transistor has a drain coupled to the data bus, a gate coupled to said bias circuit means, and a source coupled to ground, and said isolated circuit means comprises a buffer means and a second MOS transistor, said buffer means for turning ON upon receiving said high system voltage and for providing an output to a gate of said second MOS transistor, said second MOS transistor having a drain coupled to said gate of said driving MOS transistor and a source coupled to ground, wherein said second MOS transistor temporarily turns said driving MOS transistor OFF upon receiving said output of said buffer means when said buffer means is turned ON.
Claim 22
Dependent Claim
56 words
An apparatus according to claim 19, wherein: said tristate override means comprises means for preventing said second MOS transistor from turning said driving MOS transistor OFF after the electrical connector connects said transceiver to the open drain data bus, and after said bias circuit is fully powered so that it can properly control said transceiver output.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-10-22 | 2000-04-22 | 2000-10-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-10-22 | 2004-04-22 | 2004-10-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-10-22 | 2008-04-22 | 2008-10-22 | $7700.00 | Window Closed / Lapsed |