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US5334882A Expired / Lapsed US ⏱️ 0.0 years remaining

Driver for backplane transceiver logic bus

Assignee: National Semiconductor Corp
•
Filing: 1992-12-14
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Granted: 1994-08-02
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Expires: 2012-12-14
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Abstract

Abstract A driver which is particularly suitable for use with a backplane transceiver logic bus in a computer system is disclosed. In a preferred embodiment, a MOSFET is connected such that its gate and source are in a feedback loop which includes an amplifier and a first switching MOSFET. The source and drain of the MOSFET are connected in a connection path from the bus to ground, and a second switching MOSFET is connected between the gate of the MOSFET and ground. The first and second switching MOSFETS are arranged such that they switch in opposition to each other (one being turned on when the other is turned off) and a CMOS input signal is connected to the gates of the switching MOSFETS. In one state of the driver the MOSFET is turned off, in the other state the feedback loop is closed and the MOSFET is conductive. The rise and fall times of the driver's output can be controlled independently of each other.

Inventors

  • 👤 Sai L. Ting

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-26 11:34
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/003; H03K19/00346; H03K19/00361

Claims Analysis

Total Claims: 9
Claim 1
Independent Claim 108 words
A driver for a bus in a multiprocessor, said driver comprising: a transistor connected between said bus and a first reference voltage, said transistor having a first terminal and a control terminal; a feedback loop connected between said first terminal and said control terminal, said feedback loop comprising a first switching means and an amplifier, said amplifier having a first input terminal connected to said first terminal and a second input terminal connected to a second reference voltage; a second switching means connected between said control terminal and said first reference voltage; and an input to said driver connected to a control terminal of said first switching means.
Claim 2
Dependent Claim 108 words
A driver for a bus in a multiprocessor, said driver comprising: a transistor connected between said bus and a first reference voltage, said transistor having a first terminal and a control terminal; a feedback loop connected between said first terminal and said control terminal, said feedback loop comprising a first switching means and an amplifier, said amplifier having a first input terminal connected to said first terminal and a second input terminal connected to a second reference voltage; a second switching means connected between said control terminal and said first reference voltage; and an input to said driver connected to a control terminal of said first switching means.
Claim 3
Dependent Claim 23 words
The driver of claim 1 wherein said input of said driver is also connected to a control terminal of said second switching means.
Claim 4
Dependent Claim 32 words
The driver of claim 2 wherein during operation one of said first and second switching means is turned off when the other of said first and second switching means is turned on.
Claim 5
Dependent Claim 11 words
The driver of claim 1 wherein said transistor comprises a MOSFET.
Claim 6
Dependent Claim 29 words
The driver of claim 3 wherein said first switching means comprises a P-channel MOSFET, said second switching means comprises an N-channel MOSFET, and said transistor comprises an N-channel MOSFET.
Claim 7
Dependent Claim 15 words
The driver of claim 5 wherein said first reference 25 voltage is a circuit ground.
Claim 8
Dependent Claim 29 words
The driver of claim 6 comprising an inverter, said inverter being connected between said input of said driver and said control terminals of said first and second switching means.
Claim 9
Dependent Claim 21 words
The driver of claim 1 comprising a capacitor connected between said control terminal of said transistor and said first reference voltage.

References Cited (Backward Citations)

US4638186A Cited
US4866301A Cited
US5164611A Cited
US5151620A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1997-08-01 1998-01-31 1998-08-02 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2001-08-01 2002-01-31 2002-08-02 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2005-08-01 2006-01-31 2006-08-02 $7700.00 Window Closed / Lapsed

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