Patent US6239926B1 successfully refreshed from Google Patents.
Patent US5566079A successfully refreshed from Google Patents.
US5566079A
Expired / Lapsed
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Parameterized generic multiplier complier
Assignee: NXP BV
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Filing: 1992-11-12
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Granted: 1996-10-15
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Expires: 2012-11-12
Abstract
Abstract A method for producing a circuit layout comprising the steps of establishing high-level input parameters which identify input/output characteristics and high-level functional parameters of a data path, inputting the input parameters to a compiler, the compiler performing steps of creating a data path netlist by selecting data path components in response to the established high-level input parameters; and automatically selecting control logic for the data path components. The data path netlist is a high-level netlist of Boolean logic which can then easily be translated into a gate level implementation of the circuit layout.
Inventors
- 👤 Henry K. Jun
- 👤 Chun L. Liu
- 👤 Lin Yang
- 👤 Kazuyoshi Moriya
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 22:09
CPC Classifications
G; G06; G06F; G06F30/00; G06F30/30
Claims Analysis
Total Claims: 28
Claim 1
Independent Claim
141 words
A method for automatically producing a circuit layout for performing a predetermined operation using a compiler which performs the steps of: receiving established compiler input parameters; creating a data path netlist with said compiler based on said established input parameters, said step of creating further including the steps of: (a) recognizing a data format of at least one data path input; (b) selecting components from a data path library to correlate the data format of the at least one data path input to the data path; (c) selecting at least one data path component from the data path library for functional processing of said at least one data path input based on said established input parameters; and (d) selecting at least one control path component based on said selected data path component to control the at least one data path component.
Claim 2
Independent Claim
141 words
A method for automatically producing a circuit layout for performing a predetermined operation using a compiler which performs the steps of: receiving established compiler input parameters; creating a data path netlist with said compiler based on said established input parameters, said step of creating further including the steps of: (a) recognizing a data format of at least one data path input; (b) selecting components from a data path library to correlate the data format of the at least one data path input to the data path; (c) selecting at least one data path component from the data path library for functional processing of said at least one data path input based on said established input parameters; and (d) selecting at least one control path component based on said selected data path component to control the at least one data path component.
Claim 3
Dependent Claim
44 words
A method according to claim 1, wherein said input parameters are established by a designer to identify input/output characteristics of a data path, said method further including a step of: translating said data path netlist into a gate level implementation of the circuit layout.
Claim 4
Dependent Claim
68 words
A method according to claim 2, wherein said establishment of input parameters further includes the steps of: defining a number of data path inputs and outputs; defining the number of bits per word for each data path input/output; and defining a data format for each data path word by identifying whether each word is floating point or fixed point and identifying whether each word is signed or unsigned.
Claim 5
Dependent Claim
59 words
A method according to claim 2, wherein said established input parameters identify functional parameters of the data path, said method further including the steps of: specifying high-level functional processing parameters of said data path; and specifying performance parameters of the data path, said performance parameters identifying at least one of speed of operation and size of the data path.
Claim 6
Dependent Claim
38 words
A method according to claim 4, wherein said step of specifying desired functional processing parameters further includes the step of: specifying a function of adding, clipping, rounding or truncation as a high-level functional parameter of the data path.
Claim 7
Dependent Claim
43 words
A method according to claim 5, wherein said step of selecting at least one data path component from the data path library further includes the step of: automatically selecting a data path element for overflow detection if a high-level clipping function is specified.
Claim 8
Dependent Claim
53 words
A method according to claim 5, wherein said step of selecting at least one data path component from a data path library further includes the step of: selecting a high-level rounding adder instance from the data path library and an overflow instance for the rounding adder, if a high-level rounding function is specified.
Claim 9
Dependent Claim
60 words
A method according to claim 4, wherein said step of selecting at least one data path component from the data path library further includes the step of: automatically selecting overflow detection for the data path to accommodate any overflow due to data format conversion based on the number of bits in the input and output words of the data path.
Claim 10
Dependent Claim
14 words
A method according to claim 1, wherein said circuit layout includes a coefficient generator.
Claim 11
Dependent Claim
14 words
A method according to claim 1, wherein said circuit layout performs a multiplication operation.
Claim 12
Dependent Claim
14 words
A method according to claim 1, wherein said circuit layout performs a comparator operation.
Claim 13
Dependent Claim
14 words
A method according to claim 1, wherein said circuit layout performs an absolute-value operation.
Claim 14
Independent Claim
96 words
A method for producing a circuit layout for performing a predetermined operation comprising the steps of: establishing high-level compiler input parameters which identify input/output characteristics and high-level functional parameters of a data path; inputting said established input parameters to a compiler, said compiler performing the steps of: creating a high-level data path netlist by automatically selecting high-level data path components from a data path library in response to recognized data formats of said established input parameters, and by automatically selecting control logic in response to said selected data path components for controlling said data path components.
Claim 15
Independent Claim
96 words
A method for producing a circuit layout for performing a predetermined operation comprising the steps of: establishing high-level compiler input parameters which identify input/output characteristics and high-level functional parameters of a data path; inputting said established input parameters to a compiler, said compiler performing the steps of: creating a high-level data path netlist by automatically selecting high-level data path components from a data path library in response to recognized data formats of said established input parameters, and by automatically selecting control logic in response to said selected data path components for controlling said data path components.
Claim 16
Dependent Claim
50 words
A method according to claim 13, wherein said netlist of high-level data path components is a Boolean logic representation of the data path specified by said high-level input parameters, said method further including the step of: translating said data path netlist into a gate level implementation of the circuit layout.
Claim 17
Dependent Claim
66 words
A method according to claim 14, wherein said step of establishing said input parameters further includes the steps of: defining a number of data path inputs/outputs; defining a number of bits per word for each data path input/output; and defining a data format for each data path word by identifying a decimal point position for each word and identifying whether each word is signed or unsigned.
Claim 18
Dependent Claim
60 words
A method according to claim 15, wherein said established input parameters identify high-level functional parameters of the data path, said method further including the steps of: specifying high-level functional processing parameters of said data path; and specifying performance parameters of the data path, said performance parameters identifying at least one of speed of operation and size of the data path.
Claim 19
Dependent Claim
40 words
A method according to claim 16, wherein said step of specifying desired functional processing parameters further includes the step of: specifying at least a function of adding, clipping, rounding or truncation as a high-level functional parameter of the data path.
Claim 20
Dependent Claim
35 words
A method according to claim 13, wherein said step of creating a data path netlist further includes the step of: automatically selecting a data path component for overflow detection if a clipping function is specified.
Claim 21
Dependent Claim
47 words
A method according to claim 13, wherein said step of creating a data path netlist further includes the step of: automatically selecting a rounding adder component from the data path library, with an element for overflow detection of the rounding adder, if a rounding function is specified.
Claim 22
Dependent Claim
49 words
A method according to claim 13, wherein said step of creating a data path netlist further includes the step of: selecting an overflow detection for the data path to accommodate data format conversion based on a number of bits in the input and output words of the data path.
Claim 23
Dependent Claim
14 words
A method according to claim 13, wherein said circuit layout includes a coefficient generator.
Claim 24
Dependent Claim
93 words
A compiler for producing a circuit layout that performs a predetermined operation, the compiler comprising: a compiler input for receiving high-level input parameters which identify input/output characteristics and high-level functional parameters of a data path; and a compiler library of data path components for creating a high-level data path netlist by automatically selecting high-level data path components from the data path library in response to recognized data formats of the high-level input parameters, and by automatically selecting control logic in response to said selected data path components for controlling said data path components.
Claim 25
Dependent Claim
93 words
A compiler for producing a circuit layout that performs a predetermined operation, the compiler comprising: a compiler input for receiving high-level input parameters which identify input/output characteristics and high-level functional parameters of a data path; and a compiler library of data path components for creating a high-level data path netlist by automatically selecting high-level data path components from the data path library in response to recognized data formats of the high-level input parameters, and by automatically selecting control logic in response to said selected data path components for controlling said data path components.
Claim 26
Dependent Claim
64 words
A compiler according to claim 22, wherein said high-level input parameters include: a defined number of data path inputs and outputs; a defined number of bits per word for each data path input/output; and a defined data format for each data path word to identify whether each data path word is floating point or fixed point and whether each word is signed or unsigned.
Claim 27
Dependent Claim
43 words
A compiler according to claim 23 wherein said high-level input parameters further include: high-level functional processing parameters of the data path; and performance parameters of the data path to identify at least one of speed of operation and size of the data path.
Claim 28
Dependent Claim
54 words
A compiler according to claim 24, wherein said library of data path components further include: a data path element which can connect any bit line of its output bus to any bit line of its input bus, and which can set any of its output bit lines to logic zero or to logic one.
References Cited (Backward Citations)
US4703435A
Cited
US4831524A
Cited
US5150308A
Cited
US4827427A
Cited
US4922432A
Cited
US5197016A
Cited
US5005136A
Cited
US4967367A
Cited
US5224055A
Cited
US5299137A
Cited
US5287289A
Cited
US5282146A
Cited
US5278769A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-10-15 | 2000-04-15 | 2000-10-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-10-15 | 2004-04-15 | 2004-10-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-10-15 | 2008-04-15 | 2008-10-15 | $7700.00 | Window Closed / Lapsed |