Self-timed control circuit for self-resetting logic circuitry

Claim 3

The apparatus as recited in claim 1, wherein last stages in said first and second macros are operable to output said first and second data signals, and wherein said circuitry operable for causing said first and second macros to maintain active said first and second data signals until said third macro has received both said first and second data signals further comprises: circuitry operable for sensing receipt in said third macro of said first and second data signals; circuitry, coupled to said sensing circuitry, operable for signalling said first and second macros that said first and second data signals have been received by said third macro; and circuitry operable for resetting said last stages of said first and second macros in response to receipt of said signalling of said first and second macros that said first and second data signals have been received by said third macro.

Claim 4

The apparatus as recited in claim 2, wherein said circuitry operable for resetting said last stage of said first macro in response to receipt of said signalling of said first macro that said first and second data signals have been received by said third macro further comprises: circuitry operable for sensing when a next to last stage in said first macro has performed a logic operation on first data to produce second data, wherein said second data is inputted to said last stage of said first macro to produce said first data signal, wherein said circuitry operable for resetting said last stage of said first macro in response to receipt of said signalling of said first macro that said first and second data signals have been received by said third macro will not reset said last stage of said first macro until said circuitry operable for sensing when said next to last stage in said first macro has performed said logic operation on first data to produce second data has sensed said logic operation on first data.

Claim 5

The apparatus as recited in claim 3, wherein said circuitry operable for sensing receipt in said third macro of said first and second data signals includes a Mueller C-Element circuit operable for receiving first and second valid signals accompanying said first and second data signals, respectively, and wherein said circuitry, coupled to said sensing circuitry, operable for signalling said first and second macros that said first and second data signals have been received by said third macro sends a complete signal to said first and second macros in response to an output of said Mueller C-Element circuit.

Claim 6

The apparatus as recited in claim 4, wherein said circuitry operable for sensing when a next to last stage in said first macro has performed a logic operation on first data to produce second data sends an internal valid signal to said circuitry operable for resetting said last stages of said first and second macros in response to receipt of said signalling of said first and second macros that said first and second data signals have been received by said third macro, wherein said circuitry operable for resetting said last stages of said first and second macros in response to receipt of said signalling of said first and second macros that said first and second data signals have been received by said third macro comprises: a NAND gate operable for receiving said complete signal; a NOR gate having one input coupled to an output of said NAND gate and a second input operable for receiving said internal valid signal; and a one-shot pulse generator circuit coupled to an output of said NOR gate, said one-shot pulse generator circuit generating a reset signal for resetting said last stage of said first macro.

Claim 7

The apparatus as recited in claim 4, wherein said circuitry operable for resetting said first stage after said first stage has operated on said first and second data signals further comprises: a one-shot pulse generator circuit coupled to said Mueller C-Element circuit; and a switch coupled to a voltage reference, said switch coupled to said one-shot pulse generator circuit.

Claim 8

The apparatus as recited in claim 1, wherein said macros are implemented in CMOS.

Claim 9

A processor including logic circuitry, said logic circuitry comprising: a first macro operable for outputting a first data signal; a second macro operable for outputting a second data signal; a third macro coupled to said first and second macros, said third macro operable for outputting a third data signal in response to receipt of said first and second data signals from said first and second macros, wherein said first, second, and third macros each include a pipeline of self-resetting logic stages, wherein a first stage in said third macro is operable for receiving said first and second data signals, and wherein a last stage of said third macro outputs said third data signal; circuitry operable for resetting said first stage after said first stage has operated on said first and second data signals; and circuitry, coupled to said resetting circuitry, operable for causing said first and second macros to maintain active said first and second data signals until said third macro has received both said first and second data signals, wherein last stages in said first and second macros are operable to output said first and second data signals, and wherein said circuitry operable for causing said first and second macros to maintain active said first and second data signals until said third macro has received both said first and second data signals further comprises: circuitry operable for sensing receipt in said third macro of said first and second data signals; circuitry, coupled to said sensing circuitry, operable for signalling said first and second macros that said first and second data signals have been received by said third macro; and circuitry operable for resetting said last stages of said first and second macros in response to receipt of said signalling of said first and second macros that said first and second data signals have been received by said third macro, wherein said circuitry operable for resetting said last stage of said first macro in response to receipt of said signalling of said first macro that said first and second data signals have been received by said third macro further comprises: circuitry operable for sensing when a next to last stage in said first macro has performed a logic operation on first data to produce second data, wherein said second data is inputted to said last stage of said first macro to produce said first data signal, wherein said circuitry operable for resetting said last stage of said first macro in response to receipt of said signalling of said first macro that said first and second data signals have been received by said third macro will not reset said last stage of said first macro until said circuitry operable for sensing when said next to last stage in said first macro has performed said logic operation on first data to produce second data has sensed said logic operation on first data.

Claim 10

A processor including logic circuitry, said logic circuitry comprising: a first macro operable for outputting a first data signal; a second macro operable for outputting a second data signal; a third macro coupled to said first and second macros, said third macro operable for outputting a third data signal in response to receipt of said first and second data signals from said first and second macros, wherein said first, second, and third macros each include a pipeline of self-resetting logic stages, wherein a first stage in said third macro is operable for receiving said first and second data signals, and wherein a last stage of said third macro outputs said third data signal; circuitry operable for resetting said first stage after said first stage has operated on said first and second data signals; and circuitry, coupled to said resetting circuitry, operable for causing said first and second macros to maintain active said first and second data signals until said third macro has received both said first and second data signals, wherein last stages in said first and second macros are operable to output said first and second data signals, and wherein said circuitry operable for causing said first and second macros to maintain active said first and second data signals until said third macro has received both said first and second data signals further comprises: circuitry operable for sensing receipt in said third macro of said first and second data signals; circuitry, coupled to said sensing circuitry, operable for signalling said first and second macros that said first and second data signals have been received by said third macro; and circuitry operable for resetting said last stages of said first and second macros in response to receipt of said signalling of said first and second macros that said first and second data signals have been received by said third macro, wherein said circuitry operable for resetting said last stage of said first macro in response to receipt of said signalling of said first macro that said first and second data signals have been received by said third macro further comprises: circuitry operable for sensing when a next to last stage in said first macro has performed a logic operation on first data to produce second data, wherein said second data is inputted to said last stage of said first macro to produce said first data signal, wherein said circuitry operable for resetting said last stage of said first macro in response to receipt of said signalling of said first macro that said first and second data signals have been received by said third macro will not reset said last stage of said first macro until said circuitry operable for sensing when said next to last stage in said first macro has performed said logic operation on first data to produce second data has sensed said logic operation on first data.

Claim 11

The processor as recited in claim 8, further comprising: circuitry, coupled to said sensing circuitry, operable for resetting second through a next to last stages in said third macro.