US5450020A
Expired / Lapsed
US
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Self-timed digital circuits using linking circuits
Assignee: BTG International Ltd
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Filing: 1992-12-03
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Granted: 1995-09-12
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Expires: 2012-12-03
Abstract
Abstract Testing digital circuits presents problems because in operation not every "stuck at" fault is detected. The present invention provides linking circuits (12, 13, 14) and functional logic circuits (10, 11) which can be used together to provide a system which ceases operation when a "stuck at" fault occurs. Each linking circuit (12) receives a first input (16) from the output of a previous circuit (10) and a second input (15) from the output of a succeeding circuit (20), both in the vicinity of that linking circuit. The signal coding used is such that in normal operation both these inputs will be different in a predetermined way and if not it is an indication that a fault has occurred. Thus if the inputs do not exhibit the predetermined difference, the linking circuit does not pass its first input to its output. The effect is to stop the system from operating and leave it in a condition from which the location of the fault can be detected.
Inventors
- 👤 Simon R. Jones
- 👤 David W. Lloyd
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 13:39
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/003; G; G06; G06F; G06F11/00; G06F11/07; G06F11/08
Claims Analysis
Total Claims: 27
Claim 1
Independent Claim
136 words
A linking circuit for transmitting data values represented by code values, the code values being represented in the linking circuit by different states of a predetermined finite state machine, none of these states having a transition to itself, each state being represented by a combination of logic values and all transitions between states requiring a change in a predetermined number of the logic values, the linking circuit comprising first and second inputs, an output and holding means for holding a state representing a code value received at the first input if the code values applied to the first and second input represent different states of the finite state machine, and the transition to the state received from the state currently held by the holding means is a legitimate transition as defined by the finite state machine.
Claim 2
Dependent Claim
136 words
A linking circuit for transmitting data values represented by code values, the code values being represented in the linking circuit by different states of a predetermined finite state machine, none of these states having a transition to itself, each state being represented by a combination of logic values and all transitions between states requiring a change in a predetermined number of the logic values, the linking circuit comprising first and second inputs, an output and holding means for holding a state representing a code value received at the first input if the code values applied to the first and second input represent different states of the finite state machine, and the transition to the state received from the state currently held by the holding means is a legitimate transition as defined by the finite state machine.
Claim 3
Dependent Claim
70 words
A linking circuit according to claim 1 wherein the finite state machine has three states, comprising first and second states representing different respective code values which each represent data and a third state representing a further code value which represents the absence of data, and the finite state machine has transitions to and from the first and third states, and to and from the second and the third states, only.
Claim 4
Dependent Claim
55 words
A linking circuit according to claim 2 wherein the holding means is arranged to hold a code value received at the first input if the code value applied to the first input represents a data value and the code value applied to the second input represents the absence of a data value or vice versa.
Claim 5
Dependent Claim
94 words
A linking circuit according to claim 3 wherein the said inputs and outputs each have two connections, and wherein the absence of a data value is represented by the presence of first logic value at each of the two connections, a data value of zero is represented by the first logic value at one of the connections and a second logic value at the other connection, and a data value of one is represented by the second logic value at the said other connection and the first logic value at the said one connection.
Claim 6
Dependent Claim
136 words
A linking circuit according to claim 4 wherein the holding means comprises a logic gate having an input connected to the two connections of the said second input to provide the first and second logic values when the second input receives code values representing the presence and absence, respectively, of data, and first and second state-holding means each with two inputs and an output, one input being connected to the output of the logic gate, the other input being connected to a respective one of the input connections of the said first input, and the two outputs of the state holding means forming the output connections of the linking circuit, each state-holding means being arranged to set its output to one of the logic values only when that logic value is present at its two inputs.
Claim 7
Dependent Claim
15 words
A linking circuit according to claim 5 wherein the logic gate is a NOT(EXOR) gate.
Claim 8
Dependent Claim
15 words
A linking circuit according to claim 5 wherein each state-holding means is a Muller C-element.
Claim 9
Dependent Claim
29 words
A linking circuit according to claim 5 including means for setting each state-holding means to provide a selected one of the first and second logic values at its output.
Claim 10
Dependent Claim
82 words
A linking circuit according to claim 1 wherein the finite state machine has four states, each representing a code value and the machine has transitions to and from all states except where a transition would require a change in two logic values, two code values are provided for each data value and when a data value is to be transmitted immediately after the transmission of the same data value, a different code value is used from the code value used immediately before.
Claim 11
Dependent Claim
114 words
A linking circuit according to claim 9 for use where there are two data values, each of which can be represented by two of the code values formed by different combinations of two logic values, two of the code values, which represent different data values, are represented by complementary combinations of logic values, and two of the code values, which also represent different data values, are equal in that both logic values in one equal combination are the same, wherein the holding means is arranged to hold a value received at the first input if the code values received at the first and second inputs both represent complementary values or both represent equal values.
Claim 12
Dependent Claim
48 words
Apparatus including a circuit according to claim 1 and a functional logic circuit, the output of the linking circuit being coupled to the input of the functional logic circuit, or the output of the functional logic circuit being coupled to one of the inputs of the linking circuit.
Claim 13
Dependent Claim
102 words
Apparatus including at least two linking circuits according to claims 1 or 4 and at least one functional logic circuit, the linking circuits and the functional logic circuit or circuits being coupled in sequence in a signal path with the or each logic circuit between two linking circuits, each linking circuit, except the first, having its first input coupled to the output of the preceding linking circuit, and each linking circuit, except the last, having its second input coupled to the output of the succeeding linking circuit, coupling being by way of the, or one of the, functional logic circuits where required.
Claim 14
Dependent Claim
142 words
Apparatus according to claim 12 wherein the signal path divides into a number of branches at the, or one of the, functional logic circuits, there being one linking circuit preceding the functional logic circuit at which branching occurs and one linking circuit following the functional logic circuit in each branch with its first input coupled to an output of the functional logic circuit for that branch, the linking circuit preceding the functional logic circuit having one second input for each branch and connected to the output of a linking circuit in that branch, and one first input and being arranged to hold a state representing a code value received at its first input if the code values applied to all the second inputs represent data and the code value applied to the first input represents the absence of data, or vice versa.
Claim 15
Dependent Claim
83 words
Apparatus according to claim 12 wherein the signal path is one of a number of such signal paths which merge at the input to a functional logic circuit which has an input for each path to be merged coupled to the output of a last linking circuit in that path and a single output coupled to the first input of a single linking circuit, the output of the single linking circuit being coupled to the second input of each said last linking circuit.
Claim 16
Dependent Claim
52 words
An apparatus according to claim 11 wherein the functional logic circuit comprises: a logic device for carrying out a logical process, and means for ensuring that the result of the process is not output from the logic circuit until all code values applied to inputs of the logic circuit represent data values.
Claim 17
Dependent Claim
112 words
A functional logic circuit for use with a linking circuit according to claim 1 or 3 comprising logic means for carrying out a logical process, and guard means comprising first and second state holding means with outputs connected to first and second output connections of the logic circuit, respectively, wherein the guard means also comprises means for preventing the output of the logic means from appearing at the output formed by the first and second state holding means unless all code values received at all circuit inputs to the functional logic circuit represent the same state, or states separated by one state in the sequence of operation of the finite state machine.
Claim 18
Dependent Claim
61 words
A circuit comprising a linking circuit according to claim 1 and a functional logic circuit for use with linking circuits, comprising logic means for carrying out a logical process, and guard means for ensuring that the result of the process is not output from the logic circuit until all code values applied to inputs of the logic circuit representing data values.
Claim 19
Dependent Claim
154 words
A functional logic circuit for use with linking circuits, comprising: a logic means for carrying out a logical process, and guard means for ensuring that the result of the process is not output from the logic circuit until all code values applied to inputs of the logic circuit represent data values, wherein the logic means comprises one AND gate for each possible selection of input connections, in which one connection is selected from each said two-connection input to form one AND gate input, a first EXOR gate coupled to received, as inputs, the outputs of all of the said AND gates which provide a `1` for one binary data value, and a second EXOR gate coupled to receive, as inputs, the outputs of all of the said AND gates which provide a `1` for the other binary value as inputs, the outputs of the EXOR gates forming the logic outputs of the logic means.
Claim 20
Dependent Claim
154 words
A functional logic circuit for use with linking circuits, comprising: a logic means for carrying out a logical process, and guard means for ensuring that the result of the process is not output from the logic circuit until all code values applied to inputs of the logic circuit represent data values, wherein the logic means comprises one AND gate for each possible selection of input connections, in which one connection is selected from each said two-connection input to form one AND gate input, a first EXOR gate coupled to received, as inputs, the outputs of all of the said AND gates which provide a `1` for one binary data value, and a second EXOR gate coupled to receive, as inputs, the outputs of all of the said AND gates which provide a `1` for the other binary value as inputs, the outputs of the EXOR gates forming the logic outputs of the logic means.
Claim 21
Dependent Claim
87 words
A functional logic circuit for use with linking circuits, comprising: logic means for carrying out a logical process, and guard means for ensuring that the result of the process is not output from the logic circuit until all code values applied to inputs of the logic circuit represent data values, first and second output connections, and wherein the guard means comprises first and second state holding means with outputs connected to the first and second output connections, respectively, and inputs connected to outputs of the logic means.
Claim 22
Dependent Claim
87 words
A functional logic circuit for use with linking circuits, comprising: logic means for carrying out a logical process, and guard means for ensuring that the result of the process is not output from the logic circuit until all code values applied to inputs of the logic circuit represent data values, first and second output connections, and wherein the guard means comprises first and second state holding means with outputs connected to the first and second output connections, respectively, and inputs connected to outputs of the logic means.
Claim 23
Independent Claim
235 words
A method of carrying out logical processing on a succession of data values using a succession of alternating linking circuits and functional logic circuits, in which the logical processes are carried out, wherein in the circuits the code values are represented by different states of a predetermined finite state machine, none of these states having a transition to itself, each state being represented by a combination of logic values and all transitions between states requiring a change in a predetermined number of the logic values, and each circuit temporarily holds one state as it passes along the succession of circuits, comprising initialising the linking circuits to take up a different state from each adjacent linking circuit in the succession thereof, initialising each functional logic circuit to take up the same state as the preceding liking circuit, applying the data as a succession of code values to the beginning of the succession of circuits, for each linking circuit except the first, repeatedly changing the state held by that circuit to the state held by the preceding circuit if, and only if, the state held by the succeeding circuit differs from that held by the preceding circuit and the transition from the state held to the state next to be held is legitimate as defined by the finite state machine, and removing the code values at the end of the succession of circuits to output data values.
Claim 24
Independent Claim
235 words
A method of carrying out logical processing on a succession of data values using a succession of alternating linking circuits and functional logic circuits, in which the logical processes are carried out, wherein in the circuits the code values are represented by different states of a predetermined finite state machine, none of these states having a transition to itself, each state being represented by a combination of logic values and all transitions between states requiring a change in a predetermined number of the logic values, and each circuit temporarily holds one state as it passes along the succession of circuits, comprising initialising the linking circuits to take up a different state from each adjacent linking circuit in the succession thereof, initialising each functional logic circuit to take up the same state as the preceding liking circuit, applying the data as a succession of code values to the beginning of the succession of circuits, for each linking circuit except the first, repeatedly changing the state held by that circuit to the state held by the preceding circuit if, and only if, the state held by the succeeding circuit differs from that held by the preceding circuit and the transition from the state held to the state next to be held is legitimate as defined by the finite state machine, and removing the code values at the end of the succession of circuits to output data values.
Claim 25
Dependent Claim
94 words
A method according to claim 20 wherein the finite state machine has three states, comprising first and second states representing different respective code values which each represent data and a third state representing a further code value which represents the absence of data, and the finite state machine has transitions to and from the first and third states, and to and from the second and the third states, only, and in applying the code values and initialising the linking circuits, alternate code values represent the first or second state, and the third state, respectively.
Claim 26
Dependent Claim
81 words
A method according to claim 20 wherein the finite state machine has four states, each representing a code value and the machine has transitions to and from all states except where a transition would require a change in two logic values, two code values are provided for each data value and when a data value is to be transmitted immediately after the transmission of the same data value, a different code value is used from the code value used immediately before.
Claim 27
Dependent Claim
28 words
A method according to claim 20 wherein, for a transition between states in the finite state machine, the predetermined number of logic values required to change is one.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-09-11 | 1999-03-13 | 1999-09-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-09-11 | 2003-03-13 | 2003-09-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-09-11 | 2007-03-13 | 2007-09-12 | $7700.00 | Window Closed / Lapsed |