ESD protection circuit with field transistor clamp and resistor in the gate circuit of a clamp triggering FET

Claim 1

A circuit for protecting operating circuits (11) of a semiconductor chip that are connected to a pad (9) where ESD voltages may appear, the protection circuit comprising, a field transistor (20) having its channel underlying a layer of field oxide and its drain (17) connected to the pad and its source (14) connected to ground for clamping a voltage at the pad when the field transistor is turned on, a trigger FET (20) having its source (19) connected to ground and its drain (22) coupled to receive an ESD voltage at the pad, the trigger FET being subject to avalanche breakdown at ESD voltage levels, the gate oxide (24) of the trigger FET being subject to oxide breakdown at ESD voltage levels and being subject to thermal run-away when the oxide breakdown current is high, and a first resistor (31) connecting the gate electrode (26) of the trigger FET to ground to maintain the trigger FET turned off in response to signal level voltages at the pad and to turn on the trigger FET by oxide and avalanche breakdown in response to an ESD voltage at the pad and to thereby produce hole-electron pairs, the trigger FET and the field transistor being located for charge carriers from the avalanche breakdown of the trigger FET to enter the field transistor and turn it on to clamp the ESD voltage, the first resistor having a value to prevent damage to the trigger FET in the time before the field transistor has turned on and thereby preventing damage to the operating circuits or the trigger FET.