US5563099A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Metal junction method of manufacture for semiconductor devices
Assignee: Texas Instruments Inc
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Filing: 1994-08-02
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Granted: 1996-10-08
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Expires: 2014-08-02
Abstract
Abstract Via reliability failure in ULSI devices having aluminum leads is significantly reduced by forming a thin layer of metal, such as Ti, between the aluminum conductor and its antireflection coating. Heating the metal causes it to react with the aluminum and form an intermetallic coating. Via hole formation is achieved by etching. During via formation, if the etch etchs through the antireflection coating, it should stop in the intermetallic layer as opposed to etching into the underlying aluminum conductor. The thin layer of metal may be heated to form the intermetallic during planarization when curing spin on glass, or, a separate anneal may be used with planarization such as by chemical mechanical polish.
Inventors
- 👤 Carole D. Grass
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 04:08
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/40; H10W20/41; H10W20/425
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
140 words
A method of making a metal junction for a semiconductor device, comprising the steps of: forming a first metal conductor on a semiconductor wafer by providing an aluminum alloy conductor having a metal layer on it, the metal layer selected from the group consisting of Ti, Zr Hf, Cr, Mo, W, Cu, Pd, Pt, and Ni; then covering the first metal conductor with an insulator; then forming an intermetallic metal layer in the first metal conductor by heating the insulator and metal layer, the heat causing the metal layer on the aluminum alloy conductor to react with the aluminum alloy conductor and make the intermetallic metal layer; then forming an opening in the insulator, the opening terminating in the intermetallic metal layer; and forming a second metal conductor in the opening, the second metal conductor contacting the intermetallic metal layer.
Claim 2
Independent Claim
140 words
A method of making a metal junction for a semiconductor device, comprising the steps of: forming a first metal conductor on a semiconductor wafer by providing an aluminum alloy conductor having a metal layer on it, the metal layer selected from the group consisting of Ti, Zr Hf, Cr, Mo, W, Cu, Pd, Pt, and Ni; then covering the first metal conductor with an insulator; then forming an intermetallic metal layer in the first metal conductor by heating the insulator and metal layer, the heat causing the metal layer on the aluminum alloy conductor to react with the aluminum alloy conductor and make the intermetallic metal layer; then forming an opening in the insulator, the opening terminating in the intermetallic metal layer; and forming a second metal conductor in the opening, the second metal conductor contacting the intermetallic metal layer.
Claim 3
Independent Claim
114 words
A method of making an interconnect for a semiconductor device, comprising the steps of: patterning aluminum leads on a semiconductor wafer, the aluminum leads having a metal layer between an aluminum conductor and an antireflection coating; then planarizing the semiconductor wafer, where the planarizing step includes heating the semiconductor wafer, the heating causing the metal layer to react with the aluminum conductor to form an intermetallic layer between the aluminum conductor and the antireflection coating; then forming a dielectric layer on the semiconductor wafer; then etching through the dielectric layer and antireflection coating to form vias over the aluminum leads, the vias terminating in the intermetallic layer; and then filling the vias with metal.
Claim 4
Independent Claim
114 words
A method of making an interconnect for a semiconductor device, comprising the steps of: patterning aluminum leads on a semiconductor wafer, the aluminum leads having a metal layer between an aluminum conductor and an antireflection coating; then planarizing the semiconductor wafer, where the planarizing step includes heating the semiconductor wafer, the heating causing the metal layer to react with the aluminum conductor to form an intermetallic layer between the aluminum conductor and the antireflection coating; then forming a dielectric layer on the semiconductor wafer; then etching through the dielectric layer and antireflection coating to form vias over the aluminum leads, the vias terminating in the intermetallic layer; and then filling the vias with metal.
Claim 5
Dependent Claim
33 words
The method of claim 2 wherein the planarizing step includes forming spin on glass over the semiconductor wafer and curing the spin on glass by heating it between the range of 300°-400° C.
Claim 6
Dependent Claim
36 words
The method of claim 3 wherein the metal layer is between the range of 200-400 Å thick and is selected from the group consisting of Ti, Zr, Hf, Cr, Mo, W, Cu, Pd, Pt, and Ni.
References Cited (Backward Citations)
US4673592A
Cited
US4461672A
Cited
US5087591A
Cited
US4795722A
Cited
US4966865A
Cited
US5212352A
Cited
US4996133A
Cited
US5071714A
Cited
US5171642A
Cited
US5069748A
Cited
US5141897A
Cited
US5225040A
Cited
US5247204A
Cited
US5313101A
Cited
US5202579A
Cited
US5312775A
Cited
US5345108A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-10-08 | 2000-04-08 | 2000-10-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-10-08 | 2004-04-08 | 2004-10-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-10-08 | 2008-04-08 | 2008-10-08 | $7700.00 | Window Closed / Lapsed |