Semiconductor device having multilayer interconnection structure

Claim 1

A semiconductor device having a multilayer interconnection structure, comprising: a semiconductor substrate having an upper surface provided with a patterned interconnection area containing semiconductor element regions; a conductive first subbing layer deposited on said patterned interconnection area; a first interconnection layer composed of first interconnection layer portions formed on said conductive first subbing layer by plating and electrically connected to said semiconductor element regions through said conductive subbing layer; a metal connection layer composed of connection layer portions formed on said first interconnection layer portions by plating; an interlayer insulating film deposited on said first interconnection layer portions around said metal connection layer portions for burying said metal connection layer portions in such a manner that the tops of said metal connection layer portions are exposed; and a second interconnection layer composed of second interconnection layer portions deposited on said interlayer insulating film and electrically connected to said first interconnection layer portions through said metal connection layer portions, wherein said first interconnection layer has a bottom which contacts said conductive subbing layer and a top which contacts said metal connection layer portions, and said first interconnection layer portions have tapered side surfaces oriented such that said first interconnection layer portions are smaller at said top than at said bottom.